TECHNICAL DATA
IN74HC174A
Hex D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The IN74HC174A is identical in pinout to the LS/ALS174. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of six D flip-flops with common Clock and
Reset inputs. Each flip-flop is loaded with a low-to-high transition of
the Clock input. Reset is asynchronous and active-low.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC174AN Plastic
IN74HC174AD SOIC
IZ74HC174A Chip
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Reset
L
PIN 16=V
CC
PIN 8 = GND
H
H
H
H
X = Don’t care
L = LOW voltage level
H = HIGH voltage level
L
Clock
X
D
X
H
L
X
X
Output
Q
L
H
L
no change
no change
INTEGRAL
1
IN74HC174A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1,5 mm from Case for 4 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
INTEGRAL
2
IN74HC174A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
-55°C
to
25°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
40
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
≥
V
CC
-0.1 V
or
≤0.1
V
I
OUT
≤
20
µA
V
OUT
≤0.1
V
or
≥V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
IL
or V
IH
I
OUT
≤
20
µA
V
IN
= V
IL
or V
IH
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
INTEGRAL
3
IN74HC174A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, Input t
r
=t
f
=6.0 ns, V
IL
= 0 V, V
IH
=Vcc)
V
CC
Symbol
Parameter
V
Guaranteed Limit
-55°C
to
25°C
6.0
30
35
110
22
19
110
21
19
75
15
13
10
≤85°C
≤125°C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q (Figures
1 and 4)
Maximum Propagation Delay , Reset to Q
(Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Enabled
Output)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
4.8
24
28
140
28
24
140
28
24
95
19
16
10
4.0
20
24
165
33
28
160
32
27
110
22
19
10
MHz
t
PLH
, t
PHL
ns
t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
62
pF
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns, V
IL
= 0 V, V
IH
=Vcc)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, Data to
Clock (Figure 3)
Minimum Hold Time, Clock to
Data (Figure 3)
Minimum Recovery Time,
Reset Inactive to Clock (Figure
2)
Minimum Pulse Width, Clock
(Figure 1)
Minimum Pulse Width, Reset
(Figure 2)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-55
°C
to
25°C
50
10
9
5
5
5
5
5
5
75
15
13
75
15
13
1000
500
400
Guaranteed Limit
≤85°C
65
13
11
5
5
5
5
5
5
95
19
16
95
19
16
1000
500
400
≤125°C
75
15
13
5
5
5
5
5
5
110
22
19
110
22
19
1000
500
400
Unit
ns
t
h
ns
t
rec
ns
t
w
ns
t
w
ns
t
r,
t
f
ns
INTEGRAL
4
IN74HC174A
t
w
tr
CLOCK
90%
50%
10%
tf
V
CC
GND
RESET
t
PHL
Q
50%
V
CC
GND
t
w
1/fmax
t
PLH
Q
50%
10%
90%
50%
t
PHL
t
rec
CLOCK
V
CC
50%
t
TLH
t
THL
GND
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
VALID
DATA
V
CC
50%
TEST POINT
GND
t
su
t
h
V
CC
50%
DEVICE
UNDER
TEST
OUTPUT
*
C
L
CLOCK
GND
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
INTEGRAL
5
Embedded System
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