The EL4584C is a PLL (Phase Lock Loop) sub system designed
for video applications but also suitable for general purpose use
up to 36 MHz In a video application this device generates a
TTL CMOS compatible Pixel Clock (Clk Out) which is a multi-
ple of the TV Horizontal scan rate and phase locked to it
The reference signal is a horizontal sync signal TTL CMOS
format which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator An input signal
to ‘‘coast’’ is provided for applications were periodic distur-
bances are present in the reference video timing such as VTR
head switching The Lock detector output indicates correct lock
The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards by external selection of
three control pins These four ratios have been selected for com-
mon video applications including 4 F
SC
3 F
SC
13 5 MHz
(CCIR 601 format) and square picture elements used in some
workstation graphics To generate 8 F
SC
6 F
SC
27 MHz (CCIR
601 format) etc use the EL4585 which includes an additional
divide by 2 stage
For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
bypassed and an external divider chain used
FREQUENCIES and DIVISORS
Function
Divisor
PAL Fosc (MHz)
Divisor
NTSC Fosc (MHz)
3Fsc
851
13 301
682
10 738
CCIR 601
864
13 5
858
13 5
Square
944
14 75
780
12 273
4Fsc
1135
17 734
910
14 318
Applications
Pixel Clock regeneration
Video compression engine
(MPEG) clock generator
Video capture or digitization
PIP (Picture in Picture) timing
generator
Text or graphics overlay timing
Ordering Information
Part No
Temp Range Package Outline
EL4584CN -40 C to
a
85 C 16-Pin DIP MDP0031
EL4584CS -40 C to
a
85 C 16-Lead SO MDP0027
CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion
3Fsc numbers do not yield integer divisors
For 6Fsc and 8Fsc clock frequencies see
EL4585 datasheet
Connection Diagram
EL4584 SO P-DIP Packages
Demo Board
A demo PCB is available for this
product Request ‘‘EL4584 5 Demo
Board’’
February 1995 Rev B
4584 – 17
Note
All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation
4584C
1994 Elantec Inc
EL4584C
Horizontal Genlock 4 F
SC
Absolute Maximum Ratings
(T
A
e
25 C)
V
CC
Supply
Storage Temperature
Lead Temperature
Pin Voltages
Operating Ambient Temperature
Range
7V
b
65 C to
a
150 C
260 C
b
0 5V to V
CC
a
0 5V
b
40 C to
a
85 C
Operating Junction Temp
Power Dissipation
Oscillator Frequency
125 C
400 mW
36 MHz
Important Note
All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually
performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test
equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore T
J
e
T
C
e
T
A
Test Level
I
II
III
IV
V
Test Procedure
100% production tested and QA sample tested per QA test plan QCX0002
100% production tested at T
A
e
25 C and QA sample tested at T
A
e
25 C
T
MAX
and T
MIN
per QA test plan QCX0002
QA sample tested per QA test plan QCX0002
Parameter is guaranteed (but not tested) by Design and Characterization Data
Parameter is typical value at T
A
e
25 C for information purposes only
DC Electrical Characteristics
(V
DD
e
5V
Parameter
I
DD
V
IL
Input Low Voltage
V
IH
Input High Voltage
I
IL
Input Low Current
I
IH
Input High Current
I
IL
Input Low Current
I
IH
Input High Current
V
OL
Output Low Voltage
V
OH
Output High Voltage
V
OL
Output Low Voltage
V
OH
Output High Voltage
V
OL
Output Low Voltage
V
OH
Output High Voltage
I
OL
Output Low Current
I
OH
Output High Current
I
OL
I
OH
Current Ratio
I
LEAK
Filter Out
Conditions
V
DD
e
5V (Note 1)
T
A
e
25 C unless otherwise noted)
Temp
25 C
25 C
25 C
35
b
100
Min
Typ
2
Max
4
15
Test
Level
I
I
I
I
Units
mA
V
V
nA
nA
mA
mA
V
V
V
V
V
V
mA
TD is 3 5in
mA
All inputs except COAST V
IN
e
1 5V
All inputs except COAST V
IN
e
3 5V
COAST pin V
IN
e
1 5V
COAST pin V
IN
e
3 5V
Lock Det I
OL
e
1 6mA
Lock Det I
OH
e b
1 6mA
CLK I
OL
e
3 2mA
CLK I
OH
e b
3 2mA
OSC Out I
OL
e
200mA
OSC Out I
OH
e b
200mA
Filter Out V
OUT
e
2 5V
Filter Out V
OUT
e
2 5V
Filter Out V
OUT
e
2 5V
Coast Mode V
DD
l
V
OUT
l
0V
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
25 C
100
b
100
b
60
I
I
60
100
04
I
I
I
24
04
24
04
24
200
300
b
300
b
200
I
I
I
I
I
I
I
I
1 05
b
100
10
g
1
0 95
100
nA
Note 1 All inputs to 0V COAST floating
2
EL4584C
Horizontal Genlock 4 F
SC
AC Electrical Characteristics
(V
DD
e
5V
Parameter
VCO Gain
20 MHz
Conditions
Test Circuit 1
V
DD
e
5V (Note 2)
VCXO Oscillator
LC Oscillator (Typ)
Temp
25 C
25 C
25 C
25 C
35
1
10
T
A
e
25 C unless otherwise noted)
Min
Typ
15 5
Max
Test
Level
V
V
V
V
Units
dB
dB
ns
ns
TAB WIDE
H-sync S N Ratio
Jitter
Jitter
Note 2 Noisy video signal input to EL4583C H-sync input to EL4584C Test for positive signal lock
Pin Description
Pin No
16 1 2
3
4
5
6
7
Pin Name
Prog A B C
Osc VCO Out
V
DD
(A)
Osc VCO In
V
SS
(A)
Function
Digital inputs to select
d
N value for internal counter See table below for values
Output of internal inverter oscillator Connect to external crystal or LC tank VCO circuit
Analog positive supply for oscillator PLL circuits
Input from external VCO
Analog ground for oscillator PLL circuits
Charge Pump Out Connect to loop filter If the H-sync phase is leading or H-sync frequency
l
CLK
d
N current is pumped
into the filter capacitor to increase VCO frequency If H-sync phase is lagging or frequency
k
CLK
d
N
current is pumped out of the filter capacitor to decrease VCO frequency During coast mode or when
locked charge pump goes to a high impedance state
Div Select
Divide select input When high the internal divider is enabled and EXT DIV becomes a test pin
outputting CLK
d
N When low the internal divider is disabled and EXT DIV is an input from an
external
d
N
Tri-state logic input Low(
k
V
CC
)
e
normal mode Hi Z(or
High(
l
V
CC
)
e
coast mode
Horizontal sync pulse (CMOS level) input
Positive supply for digital I O circuits
Lock Detect output Low level when PLL is locked Pulses high when out of lock
TD is 3 5in
External Divide input when DIV SEL is low internal
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