PRELIMINARY
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DS80C390
Dual CAN High-Speed
Microprocessor
PIN ASSIGNMENT
48
33
FEATURES
§
80C52 compatible
−
8051 instruction-set compatible
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Four 8-bit I/O ports
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Three 16-bit timer/counters
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256 bytes scratchpad RAM
High-Speed Architecture
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4 clocks/machine cycle (8051=12)
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Runs DC to 40 MHz clock rates
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Frequency multiplier reduces EMI
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Single-cycle instruction in 100 ns
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16/32-bit math coprocessor
4 kB internal SRAM usable as
program/data/stack memory
Enhanced memory architecture
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Addresses up to 4 MB external
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Defaults to true 8051 memory compatibility
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User-enabled 22-bit program/data counter
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16-Bit/22-bit paged/22-bit contiguous
modes
−
User-selectable multiplexed / non-
multiplexed memory interface
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Optional 10 bit stack pointer
Two full-function CAN 2.0B controllers
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15 message centers per controller
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Standard 11-bit or extended 29-bit
identification modes
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Supports DeviceNet, SDS, and higher layer
CAN protocols
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Disables transmitter during autobaud
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SIESTA low power mode
Two full-duplex hardware serial ports
Programmable IrDA clock
High integration controller includes
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Power-fail reset
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Early-warning power-fail interrupt
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Programmable watchdog timer
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Oscillator-fail detection
16 total interrupt sources with 6 external
Available in 64-pin QFP, 68-pin PLCC
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DS80C390
64
17
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1
16
64-PIN QFP
9
1
61
10
60
DS80C390
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26
44
27
43
68-PIN PLCC
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110199
DS80C390
DESCRIPTION
The DS80C390 is a fast 8051-compatible microprocessor. The redesigned processor core executes 8051
instructions up to 3 times faster than the original for the same crystal speed. The DS80C390 supports a
maximum crystal speed of 40 MHz, resulting in apparent execution speeds of 100 MHz (approximately
2.5X). An optional internal frequency multiplier allows the microprocessor to operate at full speed with a
reduced crystal frequency, reducing EMI. A hardware math accelerator further increases the speed of 32
and 16 bit multiply and divide operations, as well as high-speed shift, normalization and accumulate
functions.
The DS80C390 features two full-function Controller Area Network (CAN) 2.0B controllers. Status and
control registers are distributed between SFRs and 512 bytes of internal MOVX memory for maximum
flexibility. In addition to standard 11-bit or 29-extended message identifiers, the device supports two
separate 8-bit media masks and media arbitration fields to support the use of higher-level CAN protocols
such as DeviceNet and SDS.
All of the standard 8051 resources such as three timer/counters, serial port, and four 8-bit I/O ports (plus
two 8-bit ports dedicated to memory interfacing) are included in the DS80C390. In addition it includes a
second hardware serial port, seven additional interrupts, programmable watchdog timer, brown-out
monitor, power-fail reset, and a programmable output clock that supports an IRDA interface. The device
provides dual data pointers with increment/decrement features to speed block data memory moves. It
also can adjust the speed of MOVX data memory access from two to twelve machine cycles for flexibility
in addressing external memory and peripherals.
The device incorporates a 4kB SRAM, which can be configured as various combinations of MOVX
memory, program memory, and optional stack memory. A 22-bit program counter supports access to a
maximum of 4 MB of external program memory and 4 MB of external data memory. A 10-bit stack
pointer addresses up to 1kB of MOVX memory for increased code efficiency.
A new Power Management Mode (PMM) is useful for portable or power-conscious applications. This
feature allows software to switch from the standard machine cycle rate of 4 clocks per cycle to 1024
clocks per cycle. For example, at 12 MHz standard operation has a machine cycle rate of 3 MHz. In
Power Management Mode at the same external clock speed, software can select 11.7 kHz machine cycle
rate. There is a corresponding reduction in power consumption when the processor runs slower.
The EMI reduction feature allows software to select a reduced electromagnetic interference (EMI) mode
by disabling the ALE signal when it is unneeded. The device also incorporates active current control on
the address and data buses, reducing EMI by minimizing transients when interfacing to external circuitry.
ORDERING INFORMATION
Part Number
DS80C390-QCR
DS80C390-FCR
DS80C390-QNR
DS80C390-FNR
Package
68-pin PLCC
64-pin LQFP
68-pin PLCC
64-pin LQFP
Max. Clock Speed
40 MHz
40 MHz
40 MHz
40 MHz
Temperature Range
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
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DS80C390 BLOCK DIAGRAM
Figure 1
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DS80C390
PIN DESCRIPTION Table 1
LQFP
8, 22,
40, 56
9, 25,
41, 57
46
PLCC
17, 32,
51, 68
1, 18,
35, 52
57
SIGNAL
NAME
V
CC
GND
ALE
DESCRIPTION
+5V
Digital Circuit Ground
Address Latch Enable
- Output. When the
MUX
pin is low, this
pin outputs a clock to latch the external address LSB from the
multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external transparent latch. ALE
has a pulse width of 1.5 XTAL1 cycles and a period of four
XTAL1 cycles. When the
MUX
pin is high, the pin will toggle
continuously if the ALEOFF bit is cleared. ALE is forced high
when the device is in a Reset condition or if the ALEOFF bit is set
while the
MUX
pin is high.
Program Store Enable
- Output. This signal is the chip enable for
external ROM memory.
PSEN
provides an active low pulse and is
driven high when external ROM is not being accessed.
External Access Enable
- Input. This pin must be tied to GND for
proper operation.
Multiplex/Demultiplex Select
- Input. This pin selects if the
address/data bus operates in multiplexed (
MUX
=0) or
demultiplexed (
MUX
=1) mode.
Reset
- Input. The RST input pin contains a Schmitt voltage input
to recognize external active high Reset inputs. The pin also
employs an internal pulldown resistor to allow for a combination of
wired OR external Reset sources. An RC circuit is not required for
power-up, as the device provides this function internally.
Reset Output Low
- Output. This active low signal will be
asserted:
When the processor has entered reset via the RST pin,
During crystal warm-up period following power-on or Stop mode,
During a watchdog timer reset (2 cycles duration),
During an oscillator failure (if OFDE=1),
Whenever V
CC
≤
V
RST
XTAL1, XTAL2
- Crystal oscillator pins support fundamental
mode, parallel resonant, AT cut crystals. XTAL1 is the input if an
external clock source is used in place of a crystal. XTAL2 is the
output of the crystal amplifier.
AD0-7 (Port 0)
- I/O. When the
MUX
pin is tied low, Port 0 is the
multiplexed address/data bus. While ALE is high, the LSB of a
memory address is presented. While ALE falls, the port transitions
to a bi-directional data bus. When the
MUX
pin is tied high, Port 0
functions as the bi-directional data bus. Port 0 cannot be modified
by software. The reset condition of Port 0 pins is high. No pullup
resistors are needed.
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56
PSEN
47
26
58
36
EA
MUX
2
11
RST
3
12
RSTOL
23,
24
33,
34
XTAL2,
XTAL1
55
54
53
52
51
50
49
48
67
66
65
64
63
62
61
59
AD0 / D0
AD1 / D1
AD2 / D2
AD3 / D3
AD4 / D4
AD5 / D5
AD6 / D6
AD7 / D7
DS80C390
58-64,
1
2-8, 10
P1.0-P1.7
58
59
60
61
62
63
64
1
35
36
37
38
39
42
43
44
4-7,
10-13
2
3
4
5
6
7
8
10
46
47
48
49
50
53
54
55
13-16,
19-22
A0
A1
A2
A3
A4
A5
A6
A7
A8 (P2.0)
A9 (P2.1)
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
P3.0-P3.7
Port 1
- I/O. Port 1 can function as an 8-bit bi-directional I/O port,
the non-multiplexed A0 - A7 signals (when the
MUX
pin =1), and
as an alternate interface for internal resources. Setting the SP1EC
bit relocates RXD1 and TXD1 to Port 5. The reset condition of Port
1 is all bits at logic 1 via a weak pullup. The logic 1 state also
serves as an input mode, since external circuits writing to the port
can overdrive the weak pullup. When software clears any port pin
to 0, a strong pulldown is activated that remains on until either a 1
is written to the port pin or a reset occurs. Writing a 1 after the port
has been at 0 will activate a strong transition driver, followed by a
weaker sustaining pullup. Once the momentary strong driver turns
off, the port once again becomes the output (and input) high state.
Port Alternate Function
P1.0 T2 External I/O for Timer/Counter 2
P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1 Serial Port 1 Input
P1.3 TXD1 Serial Port 1 Output
P1.4 INT2 External Interrupt 2 (Pos. Edge Detect)
P1.5
INT3
External Interrupt 3 (Neg. Edge Detect)
P1.6 INT4 External Interrupt 4 (Pos. Edge Detect)
P1.7
INT5
External Interrupt 5 (Neg. Edge Detect)
A15-A8 (Port 2)
- Output. Port 2 serves as the MSB for external
addressing. The port automatically asserts the address MSB during
external ROM and RAM access. Although the Port 2 SFR exists,
the SFR value will never appear on the pins (due to memory
access). Therefore accessing the Port 2 SFR is only useful for
MOVX A, @Ri or MOVX @Ri, A instructions, which use the Port
2 SFR as the external address MSB.
Port 3
- I/O. Port 3 functions as an 8-bit bi-directional I/O port,
and as an alternate interface for several resources found on the
traditional 8051. The reset condition of Port 1 is all bits at logic 1
via a weak pullup. The logic 1 state also serves as an input mode,
since external circuits writing to the port can overdrive the weak
pullup. When software clears any port pin to 0, the device activates
a strong pulldown that remains on until either a 1 is written to the
port pin or a reset occurs. Writing a 1 after the port has been at 0
will activate a strong transition driver, followed by a weaker
sustaining pullup. Once the momentary strong driver turns off, the
port once again becomes the output (and input) high state.
Port Alternate Function
P3.0 RXD0 Serial Port 0 Input
P3.1 TXD0 Serial Port 0 Output
P3.2
INT0
External Interrupt 0
P3.3
INT1
External Interrupt 1
P3.4 T0 Timer 0 External Input
P3.5 T1/XCLK Timer 1 External Input/External Clock Output
P3.6
WR
External Data Memory Write Strobe
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