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HY57V283220LTP-5

Description
4 banks x 1M x 32bit synchronous dram
Categorystorage    storage   
File Size902KB,15 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance
Download Datasheet Parametric View All

HY57V283220LTP-5 Overview

4 banks x 1M x 32bit synchronous dram

HY57V283220LTP-5 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeTSOP2
package instructionTSSOP, TSSOP86,.46,20
Contacts86
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time4.5 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G86
JESD-609 codee6
length22.238 mm
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width32
Number of functions1
Number of ports1
Number of terminals86
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP86,.46,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.194 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.001 A
Maximum slew rate0.23 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Bismuth (Sn/Bi)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width10.16 mm
HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No.
0.1
History
Defined Preliminary Specification
1)
2)
3)
4)
5)
6)
Modified FBGA Ball Configuration Typo.
Changed Functional Block Diagram from A10 to A11.
Changed V
DD
min from 3.0V to 3.135V.
Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.
Insert t
AC2
Value.
Insdrt t
RAS
& CLK Value.
Remark
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Defined I
DD
Spec.
Delited Preliminary.
Changed I
DD
Spec.
133MHz Speed Added
Changed FBGA Package Size from 11x13 to 8x13.
1) Changed V
DD
min from 3.135V to 3.0V.
2) Changed V
IL
min from V
SSQ
-0.3V to -0.3V.
Modified of size erra. (Page15)
(Equation :
13.00
±
10
-> 13.00
±
0.10)
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / July 2004
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