LH28F400SU-NC
4M (512K × 8, 256K × 16) Flash Memory
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
BYTE-SELECT ADDRESSES:
Selects between high and low byte when device is in
x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the
DQ
15
/A
-1
input buffer is turned off when BYTE is high).
WORD-SELECT ADDRESSES:
Select a word within one 16K block. These
addresses are latched during Data Writes.
BLOCK-SELECT ADDRESSES:
Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
LOW-BYTE DATA BUS:
Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS:
Inputs data during x16 Data Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
DQ
15
/A
-1
is address.
CHIP ENABLE INPUT:
Activate the device’s control logic, input buffers, decoders
and sense amplifiers. CE
»
must be low to select the device.
RESET/POWER-DOWN:
With RP
»
low, the device is reset, any current operation is
aborted and device is put into the deep power down mode. When the power is
turned on, RP
»
pin is turned to low in order to return the device to default con-
figuration. When the power transition is occurred, or the power on/off, RP
»
is
required to stay low in order to protect data from noise. When returning from Deep
Power-Down, a recovery time of 430 ns is required to allow these circuits to power
up. When RP
»
goes low, any current or pending WSM operation(s) are terminated,
and the device is reset. All Status registers return to ready (with all status flags
cleared). After returning, the device is in read array mode.
OUTPUT ENABLE:
Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
»
is high.
WRITE ENABLE:
Controls access to the CUI, Data Queue Registers and Address
Queue Latches. WE is active low, and latches both address and data (command or
array) on its rising edge.
READY/BUSY:
Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. When the WSM is ready for new operation or
Erase is Suspended, or the device is in deep power-down mode RY
»
/BY
»
pin is floated.
BYTE ENABLE
: BYTE low places device in x8 mode. All data is then input or
output on DQ
0
- DQ
7
, and DQ
8
- DQ
15
float. Address A
-1
selects between the high
and low byte. BYTE high places the device in x16 mode, and turns off the A
-1
input buffer. Address A
0
, then becomes the lowest order address.
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V):
For erasing memory array blocks
or writing words/bytes into the flash array.
DEVICE POWER SUPPLY (3.3 V ±0.3 V):
Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
No internal connection to die, lead may be driven or left floating.
DQ
15
- A
-1
INPUT
A
0
- A
12
A
13
- A
17
INPUT
INPUT
DQ
0
- DQ
7
INPUT/OUTPUT
DQ
8
- DQ
15
INPUT/OUTPUT
CE
»
INPUT
RP
»
INPUT
OE
»
INPUT
WE
INPUT
RY
»
/BY
»
OPEN DRAIN
OUTPUT
BYTE
INPUT
V
PP
V
CC
GND
NC
SUPPLY
SUPPLY
SUPPLY
4
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SU-NC
INTRODUCTION
Sharp’s LH28F400SU-NC 4M Flash Memory is a
revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and
communication products. With innovative capabilities,
5 V single voltage operation and very high read/write
performance, the LH28F400SU-NC is also the ideal
choice for designing embedded mass storage flash
memory systems.
The LH28F400SU-NC’s independently lockable 32
symmetrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsimile, game, PC, printer and handy terminal. The
LH28F400SU-NC’s single power supply operation en-
ables the design of memory cards which can be read/
written in 5.0 V systems. Its x8/x16 architecture allows
the optimization of memory to processor interface. The
flexible block locking option enables bundling of execut-
able application software in a Resident Flash Array or
memory card. Manufactured on Sharp’s 0.45 µm
ETOX™ process technology, the LH28F400SU-NC is
the most cost-effective, high-density 5.0 V flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
•
•
•
•
Software Locking of Memory Blocks
Memory Protection Set/Reset Capability
Two-Byte Serial Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed typically within
13 µs per byte or within 20 µs per word. A Block Erase
operation erases one of the 32 blocks in typically 0.6
seconds, independent of the other blocks.
LH28F400SU-NC allows to erase all unlocked blocks.
It is desirable in case of which you have to implement
Erase operation maximum 32 times.
Only in x8 mode, LH28F400SU-NC enables
Two-Byte Serial Write which is operated by three times
command input. Writing of memory data is performed
typically within 20 µs per two-byte. This feature can im-
prove 8-bit system write performance by up to typically
10 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) and a RY
»
/BY
»
output pin provide informa-
tion on the progress of the requested operation.
Same as the LH28F008SA, LH28F400SU-NC
requires an operation to complete before the next
operation can be requested, also it allows to suspend
block erase to read data from any other block, and
allow to resume erase operation.
The LH28F400SU-NC provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or Ap-
plication Code. Each block has an associated non-vola-
tile lock-bit which determines the lock status of the block.
In addition, the LH28F400SU-NC has a software con-
trolled master Write Protect circuit which prevents any
modifications to memory blocks whose lock-bits are set.
When the device power-up or RP
»
turns High, Write
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP
»
turns High, Erase All Un-
locked Blocks can be used. If used, Erase is performed
with reflecting actual lock status, and after that Write
and Block Erase can be used.
DESCRIPTION
The LH28F400SU-NC is a high performance 4M
(4,194,304) block erasable non-volatile random access
memory organized as either 256K × 16 or 512K × 8.
The LH28F400SU-NC includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 5.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F400SU-NC:
•
•
•
•
•
5 V Read, Write/Erase Operation (5 V V
CC
, V
PP
)
Low Power Capability
Improved Write Performance
Dedicated Block Write/Erase Protection
Command-Controlled Memory Protection
Set/Reset Capability
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash Memory.
5
DSP and ARM Processors
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