HV9931
HV9931 Unity Power Factor LED Lamp Driver
Features
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Constant output current
Large step-down ratio
Unity power factor
Low Input current harmonic distortion
Fixed frequency or fixed off-time operation
Internal 450V linear regulator
Input and output current sensing
Input current limit
Enable, PWM and phase dimming
General Description
The HV9931 is a fixed frequency PWM controller IC designed
to control an LED lamp driver using a single-stage PFC
buckboost-buck topology. It can achieve a unity power factor
and a very high step-down ratio that enables driving a single
high-brightness LED from the 85-264VAC input without a
need for a power transformer. This topology allows reducing
the filter capacitors and using non-electrolytic capacitors to
improve reliability. The HV9931 uses open-loop peak current
control to regulate both the input and the output current. This
control technique eliminates a need for loop compensation,
limits the input inrush current, and is inherently protected from
input under-voltage condition.
Capacitive isolation protects the LED Lamp from failure of the
switching MOSFET. HV9931 provides a low-frequency PWM
dimming input that can accept an external control signal with a
duty ratio of 0-100% and a frequency of up to a few kilohertz.
The PWM dimming capability enables HV9931 phase control
solutions that can work with standard wall dimmers.
Applications
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Offline LED lamps and fixtures
Street lamps
Traffic signals
Decorative lighting
Typical Application Circuit
D1
V
IN
D4
L1
C1
D2
L2
-
C
IN
~AC
~AC
R
S1
Q1
D3
R
S2
VO
+
R
ref2
R
CS1
R
ref1
R
T
VIN
GATE
CS1
GND
RT
PWMD
CS2
VDD
R
CS2
C2
HV9931
HV9931
Ordering Information
DEVICE
HV9931
Package Options
8-Lead SOIC (Narrow Body)
HV9931LG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
IN
to GND
V
DD
to GND
CS1, CS2 to GND
PWMD to GND
GATE to GND
Value
-0.5V to +470V
-0.3V to +13.5V
-0.3V to V
DD
+ 0.3V
-0.3V to (V
DD
+ 0.3V)
-0.3V to (V
DD
+ 0.3V)
Pin Configuration
VIN
1
8
RT
CS1
2
7
CS2
HV9931
GND
3
6
VDD
Continuous Power Dissipation (T
A
= +25°C)
Also limited by package power dissipation limit, whichever is lower.
GATE
4
8-Lead SOIC (derate 9mW/°C
above +25°C)
Operating temperature range
Junction temperature
Storage temperature range
5
PWMD
900mW
-40°C to +85°C
+125°C
-65°C to +150°C
8-Lead SOIC
Product Marking
YWW
Stresses beyond those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
H9931
LLLL
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
8-Lead SOIC
Electrical Characteristics
(The * denotes the specifications which apply over the full operating junction temperature range of -40°C < T
A
< +85°C, otherwise the specifications are
at T
A
= 25°C, V
IN
= 12V, unless otherwise noted)
Symbol
Input
V
INDC
I
INSD
Parameter
Input DC supply voltage range*
Shut-down mode supply
current*
Min
8
-
Typ
-
0.5
Max
450
1
Units
V
mA
Conditions
DC input voltage
PWMD connected to GND, V
IN
= 12V
Internal Regulator
V
DD
V
DD, line
V
DD, load
UVLO
∆UVLO
Internally regulated voltage*
Line regulation of V
DD
Load regulation of V
DD
V
DD
undervoltage lockout
threshold
V
DD
undervoltage lockout
hysteresis
7.12
0
0
6.45
-
7.5
-
-
6.7
500
7.88
1
100
6.95
-
V
V
mV
V
mV
V
IN
= 8, I
DD(ext)
= 0, PWMD = V
DD
,
C
GATE
= 500pF
V
IN
= 8 - 450V, I
DD(ext)
= 0, 500pF at
GATE; R
T
= 226kΩ, PWMD = V
DD
I
DD
(ext) = 0 – 1mA, 500pF at GATE;
R
T
= 226kΩ, PWMD = V
DD
V
IN
rising
---
2
HV9931
Symbol
V
PWMD(lo)
V
PWMD(hi)
R
PWMD
GATE
V
GATE(hi)
V
GATE(lo)
T
RISE
T
FALL
T
DELAY
T
BLANK
Oscillator
F
OSC
V
OFFSET1
V
OFFSET2
Initial accuracy
80
100
120
kHz
R
T
= 226KΩ
GATE high output voltage*
GATE low output voltage*
GATE output rise time
GATE output fall time
Delay from CS trip to GATE
Blanking delay
V
DD
-0.3
0
-
-
-
150
-
-
30
30
150
215
V
DD
0.3
50
50
300
280
V
V
ns
ns
ns
ns
I
GATE
= 10mA
I
GATE
= -10mA
C
GATE
= 500pF
C
GATE
= 500pF
V
IN
= 12V, V
CSI,
V
CS2
= -100mV
V
CSI,
V
CS2
= -100mV
Parameter
PWMD input low voltage*
PWMD input high voltage*
PWMD pull-down resistance
Min
-
2.4
50
Typ
-
-
100
Max
1.0
-
150
Units
V
V
kΩ
Conditions
V
IN
= 8 – 450V
V
IN
= 8 – 450V
V
PWMD
= 5V
PWM Dimming
Comparators
Comparator Input offset voltage
*
-15
-
15
mV
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Functional Block Diagram
VIN
Regulator
7.5V
VDD
CS1
Leading
Edge
Blanking
S
R Q
Osc
RT
GATE
CS2
PWMD
AGND
HV9931
3
HV9931
Typical Performance Characteristics
(T
V
DD
vs. Junction Temperature (L
IN
= 2mA)
7.7
J
= 25
O
C, V
IN
=100V unless otherwise noted)
Blanking Delay vs. Junction Temperature
300
7.65
250
200
T
BLANK
(ns)
-20
0
20
40
60
80
100
120
7.6
V
DD
(V)
150
7.55
100
7.5
50
7.45
-40
Junction Tem perature (°C)
0
-40
-20
0
20
40
60
80
100
120
Junction Tem perature (°C)
Frequency vs. Junction Temperature (R
T
= 226K)
93
8
7.5
V
DD
vs. Regulator Current (V
IN
= 100V)
92
7
Frequency (kHz)
V
DD
(V)
91
6.5
6
5.5
5
90
89
4.5
88
-40
4
-20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
18
20
Junction Tem perature (°C)
I
IN
(mA)
Functional Description
Power Topology
The HV9931 is optimized to drive Supertex’s proprietary
single-stage, single-switch, non-isolated topology, cascading
an input power factor correction (PFC) buck-boost stage
and an output buck converter power stage. This power
converter topology offers numerous advantages useful
for driving high-brightness light emitting diodes (HB LED).
These advantages include unity power factor, low harmonic
distortion of the input AC line current, and low output current
ripple. The output load is decoupled from the input voltage
with a capacitor making the driver inherently failure-safe for
the output load. The power converter topology also permits
reducing the size of a filter capacitor needed, enabling use
of non-electrolytic capacitors. The latter advantage greatly
improves reliability of the overall solution.
The HV9931 is a peak current-mode controller that is
specifically designed to drive a constant current buck-
boost-buck power converter. This patent pending control
scheme features two identical current sense comparators
for detecting negative current signal levels. One of the
comparators regulates the output LED current, while the
other is used for sensing the input inductor current. The
second comparator is mainly responsible for the converter
start-up. The control scheme inherently features low inrush
current and input under-voltage protection. The HV9931 can
operate with programmable constant frequency or constant
off-time. In many cases, the constant off-time operating mode
is preferred, since it improves line regulation of the output
current, reduces voltage stress of the power components
and simplifies regulatory EMI compliance. (See Application
Note AN-H52.)
4
HV9931
Input Voltage Regulator
The HV9931 can be powered directly from its VIN pin, and
takes a voltage from 8V to 450V. When a voltage is applied
at the VIN pin, the HV9931 seeks to maintain a constant
7.5V at the VDD pin. The V
DD
voltage can be also used as a
reference for the current sense comparators. The regulator
is equipped with an under-voltage protection circuit which
shuts off the HV9931 when the voltage at the VDD pin falls
below 6.2V.
The VDD pin must be bypassed by a low ESR capacitor
(≥ 0.1µF) to provide a low impedance path for the high
frequency current of the output gate driver.
The HV9931 can also be operated by supplying a voltage
at the VDD pin greater than the internally regulated voltage.
This will turn off the internal linear regulator and the HV9931
will function by drawing power from the external voltage
source connected to the VDD pin.
Input and Output Current Feedback
Two current sense comparators are included in the HV9931.
Both comparators have their non-inverting inputs internally
connected to ground (GND). The CS1 and CS2 inputs are
inverting inputs of the comparators. Connecting a resistor
divider into either of these inputs from a positive reference
voltage and a negative current sense signal programs the
current sense threshold of the comparator. The V
DD
voltage
of the HV9931 can be used as the reference voltage. If more
accuracy is needed, an external reference voltage can be
applied. When either the CS1 or the CS2 pin voltage falls
below GND, the GATE pulse is terminated. A leading edge
blanking delay of 215ns (typ) is added. The GATE voltage
becomes high again upon receiving the next clock pulse of
the oscillator circuit.
Referring to the Functional Circuit Diagram, the CS2
comparator is responsible for regulating output current. The
output LED current can be programmed using the following
equation:
PWM Dimming and
Wall Dimmer Compatibility
PWM Dimming can be achieved by applying a TTL-
compatible square wave signal at the PWMD pin. When the
PWMD pin is pulled high, the gate driver is enabled and the
circuit operates normally. When the PWMD pin is left open
or connected to GND, the gate driver is disabled and the
external MOSFET turns off. The HV9931 is designed so that
the signal at the PWMD pin inhibits the driver only, and the
IC need not go through the entire start-up cycle each time
ensuring a quick response time for the output current.
The power topology requires little filter capacitance at
the output, since the output current of the buck stage is
continuous, and since AC line filtering is accomplished
through the middle capacitor rather than the output one.
Therefore, disabling the HV9931 via its PWMD or VIN pins
can interrupt the output LED current in accordance with
the phase-controlled voltage waveform of a standard wall
dimmer.
R
CS 2
=
Io
+
1
∆
I
L2
2
⋅
R
REF 2
⋅
R
S 2
7
.
5V
where ∆I
L2
is the peak-to-peak current ripple in L2. The CS1
comparator limits the current in the input inductor L1. There
is no charge in the capacitor C1 upon the start-up of the
converter. Therefore, L2 cannot develop the output current,
and the HV9931 starts-up in the input current limiting mode.
The CS1 current threshold must be programmed such that no
input current limiting occurs in normal steady-state operation.
The CS1 threshold can be programmed in accordance with
a similar equation:
I
R
CS 1
=
L1
(
PK
)
⋅
R
REF 1
⋅
R
S 1
7
.
5V
where I
L1(PK)
is the maximum peak current in L1.
MOSFET Gate Driver
Typically, the gate driving capability of the HV9931 is limited
by the amount of power dissipation in its linear regulator.
Thus, care must be taken selecting a switching MOSFET
to be used in the circuit. An optimal trade-off must be found
between the gate charge and the on-resistance of the
MOSFET to minimize the input regulator current.
Oscillator
Connecting an external resistor from RT pin to GND programs
switching frequency:
25000
F
S
[
kHz
]
=
R
T
[
K
Ω
]
+
22
Connecting the resistor from RT pin to GATE programs
constant off-time:
T
OFF
[
µ
s
]
=
R
T
[
K
Ω
]
+
22
25
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