ANSALDO
Ansaldo Trasporti s.p.a.
Unita' Semiconduttori
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
PHASE CONTROL THYRISTOR
AT303
Repetitive voltage up to
Mean on-state current
Surge current
800
V
1100
A
12
kA
FINAL SPECIFICATION
feb 97 - ISSUE : 02
Symbol
Characteristic
Conditions
Tj
[°C]
150
150
150
Value
Unit
BLOCKING
V
V
V
I
I
RRM
RSM
DRM
RRM
DRM
Repetitive peak reverse voltage
Non-repetitive peak reverse voltage
Repetitive peak off-state voltage
Repetitive peak reverse current
Repetitive peak off-state current
V=VRRM
V=VDRM
800
900
800
50
50
V
V
V
mA
mA
150
150
CONDUCTING
I
I
I
V
V
r
T (AV)
T (AV)
TSM
Mean on-state current
Mean on-state current
Surge on-state current
I² t
On-state voltage
Threshold voltage
On-state slope resistance
180° sin, 50 Hz, Th=55°C, double side cooled
180° sin, 50 Hz, Tc=85°C, double side cooled
sine wave, 10 ms
without reverse voltage
On-state current =
1900 A
25
150
150
150
1100
1085
12
720 x1E3
1.45
0.8
0.340
A
A
kA
A²s
V
V
mohm
I² t
T
T(TO)
T
SWITCHING
di/dt
dv/dt
td
tq
Q rr
I rr
I
I
H
L
Critical rate of rise of on-state current, min.
Critical rate of rise of off-state voltage, min.
Gate controlled delay time, typical
Circuit commutated turn-off time, typical
Reverse recovery charge
Peak reverse recovery current
Holding current, typical
Latching current, typical
From 75% VDRM up to 1200 A, gate 10V 5ohm
Linear ramp up to 75% of VDRM
VD=200V, gate source 20V, 10 ohm , tr=.5 µs
dV/dt = 20 V/µs linear up to 80% VDRM
di/dt=-60 A/µs, I= 1000 A
VR= 50 V
VD=5V, gate open circuit
VD=12V, tp=30µs
150
150
25
150
25
25
200
500
1.5
A/µs
V/µs
µs
µs
µC
A
300
mA
mA
GATE
V
I
V
V
I
V
P
P
GT
GT
GD
FGM
FGM
RGM
GM
G
Gate trigger voltage
Gate trigger current
Non-trigger gate voltage, min.
Peak gate voltage (forward)
Peak gate current
Peak gate voltage (reverse)
Peak gate power dissipation
Average gate power dissipation
VD=5V
VD=5V
VD=VDRM
25
25
150
3.5
200
0.25
30
10
5
V
mA
V
V
A
V
W
W
Pulse width 100 µs
150
2
MOUNTING
R
R
T
F
th(j-h)
th(c-h)
j
Thermal impedance, DC
Thermal impedance
Operating junction temperature
Mounting force
Mass
ORDERING INFORMATION : AT303 S 08
standard specification
Junction to heatsink, double side cooled
Case to heatsink, double side cooled
50
15
-30 / 150
8.0 / 9.0
85
°C/kW
°C/kW
°C
kN
g
VDRM&VRRM/100
AT303 PHASE CONTROL THYRISTOR
FINAL SPECIFICATION
feb 97 - ISSUE : 02
ANSALDO
ON-STATE CHARACTERISTIC
Tj = 150 °C
SURGE CHARACTERISTIC
Tj = 150 °C
3500
3000
12
10
2500
On-state Current [A]
8
ITSM [kA]
0.6
1.1
1.6
2000
1500
1000
500
0
On-state Voltage [V]
6
4
2
0
1
10
n° cycles
100
TRANSIENT THERMAL IMPEDANCE
DOUBLE SIDE COOLED
50.0
45.0
40.0
35.0
Zth j-h [°C/kW]
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0.001
0.01
0.1
t[s]
1
10
100
Cathode terminal type DIN 46244 - A 4.8 - 0.8
Gate terminal type AMP 60598 - 1
Distributed by
All the characteristics given in this data sheet are guaranteed only with uniform
clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03
mm and roughness < 2 µm.
In the interest of product improvement ANSALDO reserves the right to change
any data given in this data sheet at any time without previous notice.
If not stated otherwise the maximum value of ratings (simbols over shaded
background) and characteristics is reported.
FPGA/CPLD
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