tm
TE
CH
T221160A
DRAM
FEATURES
64K x 16 DYNAMIC RAM
FAST PAGE MODE
PIN ASSIGNMENT ( Top View )
V cc
I/01
I/02
I/03
I/04
V cc
I/05
I/06
I/07
I/08
NC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
V ss
I/016
I/015
I/014
I/013
V ss
I/012
I/011
I/010
I/09
NC
CASL
CASH
OE
NC
A7
A6
A5
A4
VSS
•
High speed access time : 25/30/35/40 ns
•
Industry-standard x 16 pinouts and timing
functions.
•
Single 5V (±10%) power supply.
•
All device pins are TTL- compatible.
•
256-cycle refresh in 4ms.
•
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
•
Conventional FAST PAGE MODE access cycle.
•
BYTE WRITE and BYTE READ access cycles.
SO J
31
30
29
28
27
26
25
24
23
22
21
PART NUMBER EXAMPLES
PART NUMBER
R AS
NC
A0
A1
ACCESS TIME
30ns
30ns
35ns
35ns
PACKAGE
SOJ
TSOP-II
SOJ
TSOP-II
T221160A-30J
T221160A-30S
T221160A-35J
T221160A-35S
A2
A3
V cc
V cc
I/01
1
2
3
4
5
6
7
8
9
10
T S O P (II)
40
39
38
37
36
35
34
33
32
31
V ss
I/01 6
I/01 5
I/01 4
I/01 3
V ss
I/01 2
I/01 1
I/01 0
I/09
GENERAL DESCRIPTION
The T221160A is a randomly accessed solid state
memory containing 1,048,551 bits organized in a
x16 configuration. The T221160A has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode operation
The T221160A CAS function and timing are
I/02
I/03
I/04
V cc
I/05
I/06
I/07
I/08
NC
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
CA SL
CA SH
OE
NC
A7
A6
A5
A4
V SS
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (IO1~IO8), and CASH
transiting low will write data into the upper byte
(IO9~16).
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
NC
WE
RAS
NC
A0
A1
A2
A3
V cc
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
FUNCTIONAL BLOCK DIAGRAM
WE
CASL
CASH
CAS
CONTROL
LOGIC
DATA-IN BUFFER
DQ01
16
.
.
DQ16
NO.2 CLOCK
GENERATOR
DATA-
OUT
BUFFER
8
COLUM N.
ADDRESS
BUFFER
8
COLUM N
DECODER
OE
16
A0
A1
A2
A3
A4
A5
A6
A7
8
REFRESH
COUNTER
REFRESH
CONTROLLER
256
8
SENSE AM PLIFIERS
VO GATING
256 x 16
8
ROW
DECODER
8
ROW .
ADDRESS
BUFFERS(8)
8
256
256 x 256 x 16
M EM ORY
ARRA
Y
RAS
NO.1 CLOCK
GENERATOR
Vcc
Vss
PIN DESCRIPTIONS
PIN NO.
16~19,22~25
14
28
29
13
27
2~5,6~10,31~34,36~39
1,6,20
21,35,40
11,12,15,30
SYM.
A0-A7
RAS
CASH
CASL
WE
OE
I/O1 - I/O16
Vcc
Vss
NC
TYPE
Input
Input
Input
Input
Input
Input
Address Input
Row Address Strobe
Column Address Strobe /Upper Byte Control
Column Address Strobe /Lower Byte Control
Write Enable
Output Enable
DESCRIPTION
Input/ Output Data Input/ Output
Supply
Ground
-
Power, 5V
Ground
No Connect
Taiwan Memory Technology, Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS… … -1V to 7V
Operating Temperature, Ta (ambient)..0°C to +70°C
Storage Temperature (plastic)….... -55°C to +150°C
Power Dissipation ...............................…......... 1.0W
Short Circuit Output Current...................….... 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C
≤
Ta
≤
70°C; VCC = 5V
±
10 % unless otherwise noted)
DESCRIPTION
CONDITIONS
Supply Voltage
Supply Voltage
Input High (Logic) voltage
Input Low (Logic) voltage
Input Leakage Current
0V
≤
VIN
≤
7V
0V
≤
VOUT
≤
7V
Output Leakage Current
Output(s) disabled
Output High Voltage
IOH = -5 mA
Output Low Voltage
IOL = 4.2 mA
Note:
1.All Voltages referenced to Vss
SYM.
Vcc
Vss
VIH
VIL
ILI
ILO
VOH
VOL
MIN
4.5
0
2.4
-1.0
-10
-10
2.4
-
MAX
5.5
0
Vcc+1
0.8
10
10
-
0.4
UNITS
V
V
V
V
uA
uA
V
V
NOTES
1
1
1
Taiwan Memory Technology, Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
DC CHARACTERISTICS
(Ta = 0 to 70°C, Vcc = 5V
±10%,
Vss = 0V)
Parameter
Operating Current
Standby Current
Icc2
Standby Current
Fast Page Mode Current
RAS -only refresh
Current
CAS Before RAS
Refresh Current
-
4
-
4
-
4
-
4
Symbol
-25
-30
-35
-40
Unit
Test Condition
RAS , CAS cycling
tRC=min
TTL interface,
Min Max Min Max Min Max Min Max
Icc1
-
170
-
150
-
130
-
120 mA
mA RAS , CAS =VIH,
DOUT=High-Z
CMOS interface,
RAS , CAS > Vcc-0.2V
Icc3
Icc4
Icc5
Icc6
-
-
-
-
2
-
-
-
-
2
-
-
-
-
2
-
-
-
-
2
mA
170
170
170
150
150
150
130
130
130
RAS =VIL, CAS
mA
120
cycling, tPC= min
CAS =VIH, RAS
120 mA cycling, t = min
RC
120 mA
RAS , CAS cycling,
tRC= min
Note:
Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition, Icc is specified as an average current.
CAPACITANCE
(Ta =25°C, Vcc =5V, f = 1M HZ)
Parameter
Input Capacitance
(address)
Input Capacitance
( RAS , CAS , WE , OE )
Output Capacitance
(data-in/out)
Symbol
CI1
CI2
CI/O
Typ
-
-
-
Max
5
7
10
Unit
pF
pF
pF
Taiwan Memory Technology, Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
tm
TE
CH
T221160A
AC CHARACTERISTICS
(note 1,2,3) (Ta = 0 to 70°C)
AC TEST CONDITIONS:
Vcc=5V
±10%,
input pulse level = 0 to 3V
Input rise and fall times: 2ns
Output Load: 2TTL gate + CL (50pF)
AC CHARACTERISTICS
PARAMETER
Read or Write Cycle Time
Read-Modify-Write Cycle Time
Fast-Page-Mode Read or Write Cycle Time
Fast-Page-Mode Read-Write Cycle Time
Access Time From RAS
Access Time From CAS
Access Time From OE
Access Time From Column Address
Access Time From CAS Precharge
RAS Pulse Width
RAS Pulse Width
RAS Hold Time
RAS Precharge Time
CAS Pulse Width
CAS Hold Time
CAS Precharge Time
RAS to CAS Delay Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
RAS to Column Address Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference to
RAS )
Column Address to RAS Lead Time
Read Command Setup Time
SYM
tRC
tRWC
tPC
tPCM
tRAC
tCAC
tOAC
tAA
tACP
tRAS
-25
43
65
15
37
25
7
7
12
14
-30
55
85
20
42
30
8
8
16
18
-35
65
95
23
49
35
9
9
18
20
-40
75
105
25
52
40
10
10
20
22
UNIT
Notes
MIN MAX MIN MAX MIN MAX MIN MAX
ns
ns
ns
ns
ns
4
ns
5
ns
13
ns
8
ns
25 10K 30 10K 35 10K 40 10K ns
tRASC 25
100K
30
100K
35
100K
40
100K
ns
ns
tRSH
7
8
9
10
ns
tRP
15
20
23
25
tCAS
tCSH
tCP
tRCD
tCRP
tASR
tRAH
tRAD
tASC
tCAH
tAR
4
21
3
10
3
0
5
8
0
4
22
12
0
0
0
3
3
15
17
10K
6
26
3
10
3
0
5
8
0
4
26
14
0
0
0
3
3
15
21
10K
10K 10 10K ns
ns
30
35
ns
4
5
8
10
3
0
5
8
0
4
30
16
0
0
0
3
3
15
25
10
5
0
5
8
0
5
34
18
0
0
0
3
3
15
29
ns
7
ns
ns
ns
ns
8
ns
ns
ns
ns
ns
14
ns
9,14
ns
9
ns
ns
10,16
13
14
16
18
tRAL
tRCS
Read Command Hold Time Reference to CAS tRCH
Read Command Hold Time Reference to RAS tRRH
tCLZ
CAS to Output in Low-Z
Output Buffer Turn-off Delay From CAS or
RAS
tOFF1
Taiwan Memory Technology, Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
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