tm
TE
CH
T224160B
DRAM
FEATURES
•
Industry-standard x 16 pinouts and timing
functions.
•
Single 5V (
±
10%) power supply.
•
All device pins are TTL- compatible.
•
512-cycle refresh in 8ms.
•
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
•
Conventional FAST PAGE MODE access cycle.
•
BYTE WRITE and BYTE READ access
cycles.
256K x 16 DYNAMIC RAM
FAST PAGE MODE
will write data into the upper byte (IO9~16).
PIN ASSIGNMENT ( Top View )
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS
SOJ
OPTION
TIMING
30ns
35ns
45ns
60ns
PACKAGE
SOJ
TSOP(II)
MARKING
-30
-35
-45
-60
MARKING
J
S
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
1
2
3
4
5
6
7
8
9
10
TSOP(II)
40
39
38
37
36
35
34
33
32
31
Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09
GENERAL DESCRIPTION
The T224160B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224160B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode operation
The T224160B CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two
CAS
and leave the other staying high during
WRITE will result in a BYTE WRITE. CASL
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and CASH transiting low
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS
Publication Date: MAR. 2001
Revision:B
tm
TE
CH
T224160B
FUNCTIONAL BLOCK DIAGRAM
WE
CASL
CASH
CAS
CONTROL
LOGIC
DATA-IN BUFFER
DQ01
16
.
.
DQ16
NO.2 CLOCK
GENERATOR
DATA-OUT
BUFFER
9
COLUMN.
ADDRESS
BUFFER
9
COLUMN
DECODER
OE
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
9
9
ROW
DECODER
ROW.
ADDRESS
BUFFERS(9)
REFRESH
COUNTER
REFRESH
CONTROLLER
512
8
SENSE AMPLIFIERS
VO GATING
512 x 16
8
9
512
512 x 512 x 16
MEMORY
ARRAY
RAS
NO.1 CLOCK
GENERATOR
Vcc
Vss
PIN DESCRIPTIONS
PIN NO.
16~19,22~26
14
28
29
13
27
2~5,6~10,31~34,36~39
1,6,20
21,35,40
11,12,15,30
SYM.
A0-A8
RAS
CASH
TYPE
Input
Input
Input
Input
Input
Input
Supply
Ground
-
Address Input
DESCRIPTION
Row Address Strobe
Column Address Strobe /Upper Byte Control
Column Address Strobe /Lower Byte Control
Write Enable
Output Enable
Power, 5V
Ground
No Connect
CASL
WE
OE
I/O1 - I/O16
Vcc
Vss
NC
Input/ Output Data Input/ Output
Taiwan Memory Technology, Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: MAR. 2001
Revision:B
tm
1.2W
TE
CH
T224160B
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS… … -1V to 7V
Operating Temperature, Ta (ambient)..0
°
C to +70
°
C
Storage Temperature (plastic)….... -55
°
C to +150
°
C
Power Dissipation ...............................….........
Short Circuit Output Current...................…....
50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
°
C
≤
Ta
≤
70
°
C; VCC = 5V
±
10 % unless otherwise noted)
DESCRIPTION
CONDITIONS
Supply Voltage
Supply Voltage
Input High (Logic) voltage
Input Low (Logic) voltage
Input Leakage Current
0V
≤
VIN
≤
7V
0V
≤
VOUT
≤
7V
Output Leakage Current
Output(s) disabled
Output High Voltage
IOH = -5 mA
Output Low Voltage
IOL = 4.2 mA
Note:
1.All Voltages referenced to Vss
SYM.
Vcc
Vss
V IH
V IL
ILI
ILO
VOH
VOL
MIN
4.5
0
2.4
-1.0
-10
-10
2.4
-
MAX
5.5
0
Vcc+1
0.8
10
10
-
0.4
UNITS
V
V
V
V
uA
uA
V
V
NOTES
1
1
1
Taiwan Memory Technology, Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: MAR. 2001
Revision:B
tm
TE
CH
T224160B
DC CHARACTERISTICS
(Ta = 0 to 70
°
C, Vcc = 5V
±
10%, Vss = 0V)
Parameter
Operating Current
Standby Current
Icc2
Standby Current
Fast Page Mode Current
RAS -only refresh
Current
CAS Before RAS
Refresh Current
-
4
-
4
-
4
-
4
Symbol
-30
-35
-45
-60
Unit
Test Condition
RAS , CAS cycling
tRC =min
TTL interface,
Min Max Min Max Min Max Min Max
Icc1
-
200
-
180
-
160
-
140 mA
mA RAS , CAS =VIH,
DOUT=High-Z
CMOS interface,
RAS , CAS > Vcc-0.2V
RAS =VIL, CAS
cycling, tPC = min
CAS =VIH, RAS
cycling, tRC = min
RAS , CAS cycling,
tRC = min
Icc3
Icc4
Icc5
Icc6
-
-
-
-
2
200
200
200
-
-
-
-
2
180
180
180
-
-
-
-
2
160
160
160
-
-
-
-
2
mA
140 mA
140 mA
140 mA
Note:
Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition, Icc is specified as an average current.
CAPACITANCE
(Ta =25
°
C, Vcc =5V, f = 1M HZ)
Parameter
Input Capacitance
(address)
Input Capacitance
(
RAS
,
CAS
,
WE
,
OE
)
Output Capacitance
(data-in/out)
Symbol
C I1
C I2
CI/O
Typ
-
-
-
Max
5
7
10
Unit
pF
pF
pF
Taiwan Memory Technology, Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: MAR. 2001
Revision:B
tm
TE
CH
T224160B
AC CHARACTERISTICS
(note 1,2,3) (Ta = 0 to 70
°
C)
AC TEST CONDITIONS:
Vcc=5V
±
10%, input pulse level = 0 to 3V
Input rise and fall times: 2ns
Output Load: 2TTL gate + CL (50pF)
AC CHARACTERISTICS
PARAMETER
Read or Write Cycle Time
Read-Modify-Write Cycle Time
Fast-Page-Mode Read or Write Cycle Time
Fast-Page-Mode Read-Write Cycle Time
Access Time From RAS
Access Time From CAS
Access Time From OE
Access Time From Column Address
Access Time From
CAS
Precharge
RAS Pulse Width
RAS Pulse Width
RAS Hold Time
RAS Precharge Time
CAS
Pulse Width
SYM
tRC
tRWC
tPC
tPCM
tRAC
tCAC
tOAC
tAA
tACP
tRAS
-30
55
85
19
56
30
8
8
13
15
30 10K
100K
-35
65
95
21
58
35
-45
85
115
25
65
45
-60
110
155
40
80
60
15
15
30
35
60 10K
60
15
100K
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
Note
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
13
8
9
11
9
11
15
19
18
22
35 10K 45 10K
35
9
100K
tRASC 30
tRSH
8
tRP
tCAS
tCSH
tCP
tRCD
tCRP
tASR
tRAH
tRAD
tASC
tCAH
tAR
tRAL
tRCS
tRCH
tRRH
tCLZ
tOFF1
45
11
100K
25
5 10K
30
3
10
3
0
5
8
0
4
26
13
0
0
0
3
3
15
24
30
35
6 10K 7 10K
35
3
10
3
0
5
8
0
4
30
15
0
0
0
3
3
15
28
45
5
10
5
0
5
8
0
6
40
19
0
0
0
3
3
15
37
CAS Hold Time
CAS
Precharge Time
RAS to CAS Delay Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
RAS to Column Address Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference to
RAS )
Column Address to RAS Lead Time
Read Command Setup Time
Read Command Hold Time Reference to
CAS
Read Command Hold Time Reference to RAS
CAS
to Output in Low -Z
ns
40
15 10K ns
ns
60
10
20
5
0
5
15
0
15
50
30
0
0
0
3
3
15
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,16
14
9,14
9
7
17
20
26
30
8
Output Buffer Turn-off Delay From CAS or
RAS
Taiwan Memory Technology, Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: MAR. 2001
Revision:B
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