AS8202
TTP/C-C2 Communication
Controller
Preliminary Data Sheet
Rev. 1.0, October 2000
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Key Features
•
•
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•
•
•
•
•
•
•
•
•
•
•
Dedicated controller supporting TTP/C (time triggered protocol class C)
Suited for dependable distributed real-time systems with guaranteed response time
Application fields: Automotive (by-wire braking, steering, vehicle dynamics control, drive
train control), Aerospace (aircraft electronic systems), Industrial systems, Railway systems
TTP/C asynchronous data rate up to 5 MBit/s @ clock 40 MHz, synchronous data rate 25
MBit/s @ clock 40 MHz
Single power supply 3.3V
0.35µm CMOS process
Temperature range: -40°C to 125° C
2k x 16 RAM message, status and control area (communication network interface)
RAM for instruction code and configuration data
16 Bit non-multiplexed host CPU interface
16 Bit RISC architecture
16k x 16 internal FLASH memory for firmware and scheduling information
software tools, design-in support, development boards available ( http://www.tttech.com)
80 pin TQFP Package
General Description
The AS8202 communications controller is an integrated device supporting serial
communication according to the TTP/C specification. It performs all communications tasks such
as reception and transmission of messages in a TTP
®
cluster without interaction of the host
CPU.
TTP
®
provides mechanisms that allow the deployment in high-dependability distributed real-
time systems. It provides following services:
•
•
•
•
predictable transmission of messages with minimal jitter
fault-tolerant distributed clock synchronisation
consistent membership service with small delay
masking of single faults
ram_data[15:0]
ram_address[11:0]
ram_ceb
ram_oeb
ram_web
ram_readyb
time_signalb
led[0]/time_tick
led[1]/time_overflow
led[2]/microtick
xin0
xout0
resetb
plloff
rxd[1:0]
rxclk[1:0]
rxdv[1:0]
rxer[1:0]
Receiver
Controller
network
interface
(CNI)
Host
Processor
Interface
TTP/C
protocol
processor core
Bus
guardian
xin1
xout1
TTP/C
Bus -
Media
Drivers
Quartz or
Oscillator
Reset &
Time
base
Transmitter
txd[1:0]
cts[1:0]
txclk[1:0]
FLASH
memory
Instruction
RAM memory
Network
configuration
memory
(MEDL)
test_se
ftest
stest
fidis
mtest
Test
Inter-
face
Figure 1 AS8202 Block Diagram
Rev. 1.0, October 2000
Page 2 of 2
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
The CNI (communication network interface) forms a temporal firewall. It decouples the
controller network from the host subsystem by use of a dual ported RAM. This prevents the
propagation of control errors. The interface to the host CPU is implemented as 16 bit wide non-
multiplexed asynchronous bus interface.
TTP/C follows a conflict-free media access strategy called time-division-multiple access
(TDMA). This means, TTP/C deploys a time slot technique based on a global time which is
permanently synchronised. Each node is assigned a time slot in which it is allowed to perform
transmit operation. The sequence of time slots is called TDMA round, a set of TDMA rounds
forms a cluster cycle. After one cluster cycle the operation of the network repeats. The
sequence of interactions forming the cluster cycle is defined in a static time schedule, called
message-descriptor-list (MEDL). The definition of the MEDL in conjunction with the global time
determines the response time for a service request.
The membership of all nodes in the network is evaluated by the communication controller. This
information is presented in a consistent fashion to all correct cluster members. During
operation, the status of every other node is propagated within one TDMA round. The MEDL is
loaded into the configuration memory when the system starts up.
P a c k a g e a n d P i n As s i g n m e n t
Type: TQFP 80, plastic package
ram-data[7]
ram-data[6]
ram-data[5]
ram-data[4]
ram-data[3]
ram-data[2]
ram-data[1]
ram-data[0]
Vss
Vdd
ram-address[11]
ram-address[10]
ram-address[9]
ram-address[8]
ram-address[7]
ram-address[6]
ram-address[5]
Vss
ram-address[4]
ram-address[3]
60
61
Vdd
Vss
ram-data[8]
ram-data[9]
ram-data[10]
ram-data[11]
ram-data[12]
ram-data[13]
ram-data[14]
ram-data[15]
Vdd
Vss
ram-ceb
ram-oeb
ram-web
ram-readyb
to Vss
to Vdd
n.c.
n.c.
80
1
41
40
ram-address[2]
ram-address[1]
ram-address[0]
mtest
led[2]/time-overflow
led[1]/time-tick
led[0]/microtick
Vss
Vdd
time-signalb
resetb
fidis
ftest
plloff
stest
test-se
Vss
xin1
xout1
Vdd
21
AS8202
TTP/C
Communications
Controller
(TOP VIEW)
Figure 2 TQFP 80 pin package and pin assignment
Rev. 1.0, October 2000
Vdd
xout0
xin0
Vss
txd[0]
cts[0]
txclk[0]
rxer[0]
rxclk[0]
rxdv[0]
rxd[0]
Vdd
Vss
txd[1]
cts[1]
txclk[1]
rxer[1]
rxclk[1]
rxdv[1]
rxd[1]
20
Page 3 of 3
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Pin Description
Pin
1,12,21,32,51,61,71
4,13,24,33,43,52,62,72
2
3
5
6
7
8
9
10
11
14
15
16
17
18
19
20
22
23
Name
Vdd
Vss
xout0
xin0
txd[0]
cts[0]
txclk[0]
rxer[0]
rxclk[0]
rxdv[0]
rxd[0]
txd[1]
cts[1]
txclk[1]
rxer[1]
rxclk[1]
rxdv[1]
rxd[1]
xout1
xin1
Dir
P
P
O
I
O
PU
O
PD
I
PD
I
PU
I
PD
I
PU
I
PU
O
PU
O
PD
I
PD
I
PU
I
PD
I
PU
I
PU
O
I
Description
positive power supply
Negative power supply
Main clock: analog pad from oscillator / leave open
when providing external clock
Main clock: analog pad from oscillator / use as input
when providing external clock
Transmit data channel 0
Transmit enable channel 0
TTP/C synchronous: Transmit clock channel 0
TTP/C synchronous: Receive error channel 0
TTP/C synchronous: Receive clock channel 0
TTP/C synchronous: Receive data valid channel 0
Receive data channel 0
Transmit data channel 1
Transmit enable channel 1
TTP/C synchronous: Transmit clock channel 1
TTP/C synchronous: Receive error channel 1
TTP/C synchronous: Receive clock channel 1
TTP/C synchronous: Receive data valid channel 1
Receive data channel 1
Bus guardian clock: analog pad from oscillator / leave
open when providing external clock
Bus guardian clock: analog pad from oscillator / use as
input when providing external clock
Test input, connect to Vss
Test input, connect to Vss
PLL disable pin
Test input, connect to Vss
Test input, connect to Vss
main reset input signal, active low
CNI control signal, CNI time signal
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_TICK
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
Test input, connect to Vss
Host interface (CNI) address bus
Host interface (CNI) data bus, tristate
Host interface (CNI) chip enable, active low
Host interface (CNI) output enable, active low
Host interface (CNI) write enable, active low
Host interface (CNI) transfer finish signal, active low
Connect to Vss
Connect to Vdd
Do not connect
Do not connect
Input CMOS with pull up
Output CMOS
Output with pull up when tristate
Power Pin
25
26
27
28
29
30
31
34
35
36
37
38-42,44-50
53-60,63-70
73
74
75
76
77
78
79
80
I
I
PD
O
PD
I/O
test_se
stest
plloff
ftest
fidis
resetb
time_signalb
led[0]/microtick
led[1]/time_tick
led[2]/time_overflow
mtest
ram_address[0:11]
ram_data[0:15]
ram_ceb
ram_oeb
ram_web
ram_readyb
to Vss
to Vdd
high Z
high Z
I
PD
I
PD
I
PD
I
PD
I
PD
I
O
PU
O
PD
O
PD
O
PD
I
PD
I
I/O
I
PU
I
PU
I
PU
O
PU
P
I
PU
Input CMOS
Input CMOS with pull down
Output with pull down when tristate
Input/Output CMOS tristate
I
PU
O
O
PU
P
Rev. 1.0, October 2000
Page 4 of 4
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Electrical Specifications
Absolute Maximum Ratings (Non Operating)
SYMBOL
VDD
V
in
I
in
T
strg
T
sold
t
sold
H
ESD
1.
PARAMETER
DC Supply Voltage
Input Voltage on any Pin
Input Current on any Pin
Storage Temperature
Soldering Temperature
Soldering Time
Humidity
Electrostatic Discharge
MIN
-0.3 V
- 0.3 V
-100 mA
-55 oC
MAX
5.0 V
VDD + 0.3 V
100 mA
150 oC
260 oC
10 sec
85 %
NOTE
25°C
1)
Reflow and Wave
HBM: R = 1.5 k , C = 100 pF
5%
1000 V
300 oC all ceramic packages and DIL plastic packages, 260 oC for surface mounting plastic packages
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may effect device reliability (e.g. hot carrier
degradation).
Recommended Operating Conditions
PARAMETER
DC Supply Voltage
Circuit Ground
Static Supply Current
Operating Supply Current
Main clock frequency
Bus Guardian clock
frequency
Ambient Temperature
1.
SYMBOL
VDD
VSS
IDDS
IDD
CLK
CLK2
Ta
MIN
3.0 V
0.0 V
----
----
5 MHz
4 MHz
-40 oC
TYP
3.3 V
0.0 V
700
µ
A
45 mA
MAX
3.6 V
0.0 V
800
µ
A
56 mA
20 MHz
16 MHz
+125 oC
NOTE
1)
2)
fCLK = 40 MHz, VDD = 3.6 V
3)
oscillator pins xin0, xout0
oscillatpr pins xin1, xout1
1)
2.
3.
The input and output parameter values in this table are directly related to ambient temperature and DC supply
voltage. A temperature range other Ta
min
to Ta
max
or a supply voltage range other than VDD
min
to VDD
max
will
affect these values and must be evaluated extra.
Static supply current IDDS is exclusive of input/output drive requirements and is measured at maximum VDD
with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current.
Operating current is exclusive of input/output drive requirements and is measured at maximum VDD and
maximum clock frequency 40 MHz.
DC Characteristics and Voltage Levels
CMOS I/O levels for specified voltage and temperature range unless otherwise noted.
Inputs Pins
Pin Name
All inputs and IO pins
without pull-up/down
Inputs with pull-up
Inputs with pull-down
1.
2.
3.
Vil
max
30%
VDD
30%
VDD
30%
VDD
Vih
min
70%
VDD
70%
VDD
70%
VDD
Iil (1)
min
NA
-50
µ
A
NA
max
-1.0
µ
A
-160
µ
A
NA
Iih(2)
min
NA
NA
30
µ
A
NOTE
max
1.0
µ
A
NA
160
µ
A
CMOS input (3)
CMOS with
pull up (3)
CMOS with
pull down (3)
Iil ist tested at VDDmax and Vin = 0
Iih ist tested at VDDmax and Vin = VDDmax
CMOS input levels are in percentage of VDD, for pull-up/down refer to pin description above.
Rev. 1.0, October 2000
Page 5 of 5
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