SMS64
Six-Channel Supply Monitor and Sequencing Controller
FEATURES & APPLICATIONS
•
Monitors and Controls up to 6 Power
Supplies
•
Programmable Sequencing for both Power-
on and Power-off
•
Programmable Threshold Sensors
•
Programmable Reset and Interrupt Functions
•
Programmable Watchdog/Longdog Timer
•
Fault and Status Registers
•
4k-Bit Nonvolatile Memory
Applications
•
Monitor and Control Distributed Power and
Point of Use Power Supplies
•
Telecom
•
Compact PCI
•
Servers
•
Multi-voltage Network Processors, DSPs,
ASICs
Preliminary
INTRODUCTION
The SMS64 is a highly integrated power supply
monitor and controller. The SMS64 has six supply
managers, each individually programmable with
regard to threshold voltages, actions that can be taken
with either an under- or over-voltage condition and
how that manager will operate in sequencing the
power-on operation.
The managers can act independently or sequenced
with any other manager in the device. When the
managers work together the device can control the
sequence in which power is applied to the application
circuits. Each manager is assigned to a sequence
position which allows the device to perform power
supply sequencing in any order.
For power-off
situations the SMS64 can sequence the supplies
either in the same order or reverse order from the
power-on sequence.
The SMS64 has two programmable Watchdog
timers, two programmable reset outputs and a
programmable IRQ# output. Using the I
2
C 2-wire
serial interface, a host system can communicate with
the SMS64 status register, optionally control power-on
via software and utilize 4 K-bits of nonvolatile memory.
SIMPLIFIED APPLICATIONS DRAWING
3.3V
V+
OU T
2.5V
ON/OFF
SET
GND
UP
2.7V
2.7V
V+
OU T
1.8V
VCC
A
PUP
A
PUP
B
PUP
C
VM
A
VCC
B
VM
B
RESET#
Pow er-On
MR#
VM
C
VM
D
PW R_ON /O FF
VCC_CAP
T
G_ HY#
CA
P
PUP
D
SHDN SET
GND
ASIC
SM S64
RST_B#
PUP
E
PUP
F
GN
AL
IR Q
HE
IRQ#
HEALTHY#
GND
V+
OU T
GND
ON/OFF
VG
VM
F
VM
E
D
RST_A#
#
2.0V
DSP
2.7V
V+
OU T
GND
ON/OFF
1.5V
Power Supply Sequencing and System Start-up Initialization using the SMS64
This is an example application and the specific component values are purposely not shown. The SMS64 can be used with any combination of
MOSFETs, LDOs or DC/DC converters to optimize sequencing and minimize losses in the power chain.
©
SUMMIT MICROELECTRONICS, Inc. 2003 • 1717 Fox Dr. • San Jose, CA 95131 • Phone 408-436-9890 • FAX 408-436-9897 •
wwwsummitmicro.com
Characteristics Subject to Change Without Notice
2060 2.22 10/09/03
1
SMS64
Preliminary
3.3V
2.7V
2.5V
2.0V
1.8V
1.5V
RST_A#
RST_B#
---
t2
---
Figure 1 – Example Power Supply Sequencing and System Start-up Initialization using the SMS64 as
shown in the Simplified Applications Drawing on page 1. Any order of supply sequencing can be applied
using the SMS64
GENERAL DESCRIPTION
The SMS64 has four major functional blocks; the
supply managers and the sequencing outputs; the
programmable reset and interrupt circuitry; the timing
and control block; and the nonvolatile memory array.
The managers are comprised of a voltage monitor
with a programmable threshold input. The monitored
voltage threshold can be programmed anywhere
between 0.9V and 6.0V in 20mV increments. Each
monitor provides an under-voltage/over-voltage
(UV/OV) signal to the internal bus.
Associated with each monitor is an output circuit
(PUP circuit) that can be used to enable or switch an
external power supply to the application’s circuits. The
point in time and position in a sequence when the
output is asserted is programmable and is controlled
by the sequence position assignments and the PUP
delays in the timing and control block.
The other major block is a programmable reset and
interrupt block. The SMS64 provides a great deal of
flexibility in choosing the trigger source for the resets
and interrupt.
The sources include multiple
combinations of UV/OV conditions, and programmable
Watchdog and Longdog timers.
Programming of the SMS64 is performed over the
industry standard I
2
C, 2-wire serial data interface. It
allows configuration of the device, real-time control of
the power-on/power-off processes and instant-access
to the power supply status of the application circuit.
The bus interfaces the host to 4k bits of nonvolatile
memory and the programmable configuration
registers.
Summit Microelectronics, Inc
2060 2.22 10/09/03
2
SMS64
Preliminary
FUNCTIONAL BLOCK DIAGRAM
PW R_ON/OFF
17
VCC_CAP
VCC_CAP
FS#
16
UV/OV
A
VCC
A
VM
A
6
31
Voltage
Monitor A
PUP
Control A
46
PUP
A
UV/OV
B
VCC
B
VM
B
5
32
Voltage
Monitor B
Sequence
Control
UV/O V
C
PUP
Control B
45
PUP
B
VCC
C
VM
C
4
33
Voltage
Monitor C
PUP
Control C
43
PUP
C
SCL
SDA
A1
A2
CS#
13
14
11
10
12
27
100K
100K
100K
I C Serial
Interface
2
RST_A#
RST_B#
M R#
W LDI
IRQ#
HEALTHY#
Mem ory
Array
Reset and
Interrupt
Control
Logic
26
100K
18
30
25
28
VCC_CAP
VGG_CAP
7
37
Pow er
Supply
Arbitration
UV/OV
D
VCC
D
VM
D
3
34
Voltage
Monitor D
PUP
Control D
42
PUP
D
UV/O V
E
VCC
E
VM
E
2
35
Voltage
Monitor E
PUP
Control E
41
PUP
E
UV/OV
F
VCC
F
VM
F
1
36
Voltage
Monitor F
PUP
Control F
40
PUP
F
15
24
GND GND
Summit Microelectronics, Inc
2060 2.22 10/09/03
3
SMS64
Preliminary
PIN DESCRIPTIONS
PIN DESCRIPTIONS
Pin
Number
6
5
4
3
2
1
7
10
11
12
Pin
Type
PWR
PWR
PWR
PWR
PWR
PWR
PWR
I
I
I
Pin Name
VCC
A
VCC
B
VCC
C
VCC
D
VCC
E
VCC
F
VCC_CAP
A2
A1
CS#
Pin Description
The VCC inputs have two functions on the SMS64. They are used as the
power supply inputs and as such are diode-OR’ed so that at any point in time the
highest potential input will be the power source for the SMS64. So long as one of
the inputs is at or above 1V the RESET outputs will be active. For proper device
operation, including sequencing, at least one of the pins must be at or above
2.7V.
Each VCC input can be programmed as a voltage sensing input. It will only be
used as a precursor to power-on sequencing. Once it reaches its V
PTH
the
comparator’s source input will be switched to its corresponding VM input.
VCC_CAP is a charge storage connection to the SMS64’s internal power
supply. For most applications this pin is tied to a 10µF capacitor.
The address pins are biased either to VCC_CAP or GND.
When
communicating with the SMS64 over the 2-wire bus these pins provide a
mechanism for assigning a unique bus address. A2 and A1 are internally
connected to VCC through a 100KΩ resistor.
The Chip Select input is used solely for enabling communication on the 2-wire
bus. In order to write or read the registers or the memory array the CS# input
must be low. CS# is internally connected to VCC through a 100KΩ resistor.
The SCL input is used to clock data into and out of the memory array. In the
write mode, data must remain stable while SCL is HIGH. In the read mode, data
is clocked out on the falling edge of SCL.
SDA is the bidirectional serial data pin. It is configured as an open drain
output and will require a pull-up resistor to VCC_CAP or a higher potential system
supply.
GND is the ground for both the analog and digital portions of the internal
circuitry. It is internally tied to pin 24. (Both pins should be tied to system ground).
The force shutdown input is used to immediately turn off all PUP outputs. FS#
is internally connected to VCC through a 100KΩ resistor.
The PWR_ON/OFF input is used to initiate power-on and power-off
sequencing. When the input is high and all of the programmed preconditions are
met, the SMS64 will power-on.
If the input is taken low, the SMS64 will begin the power-off operation. If
programmed to do so, the SMS64 will sequence off the PUP outputs either in the
power-on order or reverse order. PWR_ON/OFF is internally connected to VDD
through a 100KΩ resistor.
MR# is the manual reset input. When MR# is taken low the RST_A# and
RST_B# outputs will be driven low. The RST outputs will stay low so long as the
MR# input is low, and will remain low for t
PRTO
after MR# returns high (so long as
no other reset conditions exist).
MR# must be low in order to write to the configuration registers and
high to
write to the memory array (see descriptions on page 16).
MR# is internally
connected to VCC through a 100kΩ pull-up resistor.
13
I
SCL
14
15
16
I/O
PWR
I
SDA
GND
FS#
17
I
PWR_
ON/OFF
18
I
MR#
Summit Microelectronics, Inc
2060 2.22 10/09/03
4
SMS64
Preliminary
PIN DESCRIPTIONS CONT’D
Pin
Number
24
Pin
Type
PWR
Pin Name
GND
Pin Description
GND is the ground for both the analog and digital portions of the internal
circuitry. It is internally tied to pin 15. (Both pins should be tied to system ground).
The interrupt output is an active low open-drain output. It will be driven low
whenever the Watchdog timer times out or whenever an enabled under-voltage or
over-voltage condition on a VM input exists.
The IRQ# signal is held in an inactive state during the power-on and
power-off sequence.
During the power-on sequence RST_B# will be asserted (driven low) until the
entire power-on sequence has been completed and the programmable reset
interval timer (tPRTO) has elapsed.
RST_B# will be forced low by asserting the MR# input. It will remain low so long
as the MR# input is low plus the programmed reset time out period for RST_B#.
RST_B# will be asserted whenever an enabled UV/OV condition exists.
RST_B# will remain active so long as the UV/OV condition exists and t
PRTO
expires.
The RST_B# is an active low open drain output.
During the power-on sequence RST_A# will be driven low and will remain low
until a selected PUP output has become active. and the triggers for RST_A# are
inactive. In this manner the RST_A# can be used to release a portion of the circuitry
from reset before the entire system is energized.
RST_A# will be forced low by asserting the MR# input. It will remain low so long
as the MR# input is low plus the programmed reset time out period for RST_A#.
RST_A# will be asserted whenever an enabled UV/OV condition exists.
RST_A# will remain active so long as the UV/OV condition exists and t
PRTO
expires.
The RST_A# is an active low open drain output.
The healthy output is used to signal that the VM inputs are not generating any
under-voltage or over-voltage conditions.
WLDI is the Watchdog and Longdog timers’ interrupt input. A low to high
transition on the WLDI input will clear both the Watchdog and Longdog timers,
effectively starting a new time-out period.
If WLDI is stuck low and no low-to-high transition is received within the
programmed t
PWDTO
period (programmed watch dog time-out) IRQ# will be driven
low. If a transition is still not received within the programmed t
PLDTO
period
(programmed Longdog time-out) RESET# will be driven low. Refer to Figure 5 for a
detailed illustration.
Holding WLDI high will block interrupts from occurring but will not block the
Longdog from timing out and generating a reset. Refer to Figure 3 for a detailed
illustration of the relationship between IRQ#, RESET#, and WLDI.
25
O
IRQ#
26
O
RST_B#
27
O
RST_A#
28
O
HEALTHY#
30
I
WLDI
31
32
33
34
35
36
I
I
I
I
I
I
VM
A
VM
B
VM
C
VM
D
VM
E
VM
F
The VM pins are the voltage monitor inputs. The input voltage is either
compared to a programmed threshold voltage (V
PTH
) or it can be compared to a
preset reference voltage of 0.5V.
Summit Microelectronics, Inc
2060 2.22 10/09/03
5
FPGA/CPLD
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