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PCR06A

Description
silicon planar pnpn thyristor
File Size223KB,3 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

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silicon planar pnpn thyristor

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO.,LTD
TO-92 Plastic-Encapsulate Transistors
PCR 0.6 A
FEATURES
Silicon Planar pnpn Thyristor
TO—92
1.CATHODE
 Current-I
GT
:120
μ
A
I
TRMS
:
V
DRM
:
0.6A
400V
2.GATE
3.ANODE
1 2 3
Operating and storage junction temperature range
T
J
,T
stg
: -55℃ to +150℃
ELECTRICAL CHARACTERISTICS(Tamb=25℃
Parameter
On state voltage
Gate trigger voltage
Repetitive peak off-state voltage
Symbol
V
TM
V
GTF
V
DRM
unless
Test
otherwise
specified)
MIN
MAX
1.7
0.8
400
UNIT
V
V
V
conditions
I
TM
=0.6A
V
AK
=7V
I
DRM
= 10
μA
Holding current
I
H
A2
A1
A-1
I
HL
= 20 mA ,
Av = 7 V
5
15
30
5
15
30
45
60
80
120
mA
µA
µA
µA
µA
µA
µA
Gate trigger current
I
GTF
A-2
A
B
V
AR
=7V
45
60
80
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