IN74ACT193
P
RESETTABLE
4-B
IT
B
INARY
UP/DOWN C
OUNTER
High-Speed Silicon-Gate CMOS
The IN74ACT193 is identical in pinout to the LS/ALS192,
HC/HCT192. The IN74ACT193 may be used as a level converter
for interfacing TTL or NMOS outputs to High Speed CMOS inputs.
The counter has two separate clock inputs, a Count Up Clock
and Count Down Clock inputs. The direction of counting is
determined by which input is clocked. The outputs change state
synchronous with the LOW-to-HIGH transitions on the clock
inputs. This counter may be preset by entering the desired data on
the P0, P1, P2, P3 input. When the Parallel Load input is taken
low the data is loaded independently of either clock input. This
feature allows the counters to be used as devide-by-n by
modifying the count lenght with the preset inputs. In addition the
counter can also be cleared. This is accomplished by inputting a
high on the Master Reset input. All 4 internal stages are set to low
independently of either clock input.Both a Terminal Count Down
(TC
D
) and Terminal Count Up (TC
U
) Outputs are provided to
enable cascading of both up and down counting functions. The
TC
D
output produces a negative going pulse when the counter
underflows and TC
U
outputs a pulse when the counter
overflows. The counter can be cascaded by connecting the
TC
U
and TC
D
outputs of one device to the Count Up Clock and
Count Down Clock inputs, respectively, of the next device.
•
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
µA;
0.1
µA
@ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT193N Plastic
IN74ACT193D SOIC
T
A
= -40° to 85° C for all
packages
PIN ASSIGNMENT
•
•
•
•
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
1
IN74ACT193
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
mA
±20
I
OUT
DC Output Sink/Source Current, per Pin
mA
±50
I
CC
DC Supply Current, V
CC
and GND Pins
mA
±50
P
D
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
T
L
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
V
CC
DC Supply Voltage (Referenced to GND)
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to
GND)
T
J
Junction Temperature (PDIP)
T
A
Operating Temperature, All Package Types
I
OH
Output Current - High
I
OL
Output Current - Low
t
r
, t
f
Input Rise and Fall Time
*
V
CC
=4.5 V
V
CC
=5.5 V
(except Schmitt Inputs)
*
V
IN
from 0.8 V to 2.0 V
Min
4.5
0
Max
5.5
V
CC
140
+85
-24
24
10
8.0
Unit
V
V
°C
°C
mA
mA
ns/V
-40
0
0
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, V
IN
and
V
OUT
should be constrained to the range GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
V
CC
). Unused outputs must be left open.
2
IN74ACT193
DC ELECTRICAL CHARACTERISTICS(Voltages
Referenced to GND)
V
C
Guaranteed Limits
C
Symbol
V
IH
Parameter
Test Conditions
V
25
°C
Minimum
High- V
OUT
=0.1 V or V
CC
-0.1 V 4.5
2.0
Level
Input
5.5
2.0
Voltage
V
IL
Maximum Low - V
OUT
=0.1 V or V
CC
-0.1 V 4.5
0.8
Level
Input
5.5
0.8
Voltage
V
OH
Minimum
High- I
OUT
≤
-50
µA
4.5
4.4
Level
Output
5.5
5.4
Voltage
*
V
IN
=V
IH
or V
IL
3.86
4.5
I
OH
=-24 mA
4.86
5.5
I
OH
=-24 mA
V
OL
Maximum
Low- I
OUT
≤
50
µA
4.5
0.1
Level
Output
5.5
0.1
Voltage
*
V
IN
=V
IH
0.36
4.5
I
OL
=24 mA
0.36
5.5
I
OL
=24 mA
I
IN
Maximum Input V
IN
=V
CC
or GND
5.5
±0.1
Leakage Current
V
OLD
=1.65 V Max
I
OLD
+Minimum
5.5
Dynamic Output
Current
V
OHD
=3.85 V Min
I
OHD
+Minimum
5.5
Dynamic Output
Current
V
IN
=V
CC
or GND
I
CC
Maximum
5.5
8.0
Quiescent Supply
Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Inputs
PL
CP
U
-40°C to
85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
75
-75
80
Unit
V
V
V
V
µA
mA
mA
µA
MR
CP
D
X
X
H
H
H
X
L
L
L
H
L
H
L
H
L
H
X = don’t care
X
X
H
H
FUNCTION TABLE
Mode
The IN74ACT193 is an UP/DOWN MODULO-16
Binary Counter.
Logic equations
For Terminal Count:
Reset(Asyn.)
Preset(Asyn.)
TC
U
= Q
0
•
Q
1
•
Q
2
Q
3
•
CP
U
No Count
TC
D
=
Q
0
•
Q
1
•
Q
2
•
Q
3
•
CP
D
Count Up
Count Down
No Count
3
IN74ACT193
AC ELECTRICAL CHARACTERISTICS(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Unit
Symbol
Parameter
25
°C
-40°C to
85°C
Min Max Min Max
f
max
Maximum Clock Frequency (Figure 1)
100
80
MHz
t
PLH
15
16.5
ns
Propagation Delay, CP
U
or CP
D
to
TC
U
or
TC
D
(Figure 2)
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
C
IN
Propagation Delay, CP
U
or CP
D
to
TC
U
or
14
12
12
12
12
12
15
15
14
14
15
11
15
15
4.5
15.5
13.5
13.5
13.5
13.5
13.5
16.5
16.5
15.5
15.5
16.5
12.5
16.5
16.5
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
TC
D
(Figure 2)
Propagation Delay, CP
U
or CP
D
to Q
n
(Figure 1)
Propagation Delay, CP
U
or CP
D
to Q
n
(Figure 1)
Propagation Delay, P
n
to Q
n
(Figure 3)
Propagation Delay, P
n
to Q
n
(Figure 3)
Propagation Delay, PL to Q
n
(Figure 4)
Propagation Delay, PL to Q
n
(Figure 4)
Propagation Delay, MR to Q
n
(Figure 5)
Propagation Delay, MR to TC
U
(Figure 6)
Propagation Delay, MR to TC
D
(Figure 6)
Propagation Delay, PL to
TC
U
or
TC
D
(Figure 6)
Propagation Delay, PL to
TC
U
or
TC
D
(Figure 6)
Propagation Delay, P
n
to
TC
U
or
TC
D
(Figure 6)
Propagation Delay, P
n
to
TC
U
or
TC
D
(Figure 6)
Maximum Input Capacitance
C
PD
Power Dissipation Capacitance
Typical @25°C,V
CC
=5.0
V
45
pF
4
IN74ACT193
TIMING REQUIREMENTS(C
L
=50pF, Input t
r
=t
f
=3.0 ns, V
CC
=5.0 V
±
10%)
Guaranteed Limits
Symbol
Parameter
25
°C
-40°C to
85°C
t
su
Minimum Setup Time, P
n
to PL (Figure 7)
8
9
t
h
Minimum Hold Time, PL to P
n
(Figure 7)
-1.0
-1.0
t
w
Minimum Pulse Width, PL (Figure 4)
14
15
t
w
Minimum Pulse Width, CP
U
or CP
D
10
11
(Figure 1)
t
w
Minimum Pulse Width, MR (Figure 5)
12
14
t
rec
Minimum Recovery Time, PL to CP
U
or CP
D
8
9
(Figure 5)
t
rec
Minimum Recovery Time, MR to CP
U
or
14
16
CP
D
(Figure 5)
Unit
ns
ns
ns
ns
ns
ns
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
5
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