Freescale Semiconductor, Inc.
Technical Data
DSP56362/D
Rev. 3, 02/2004
24-Bit Audio Digital
Signal Processor
Freescale Semiconductor, Inc...
Motorola designed the DSP56362 to support digital audio applications requiring digital audio compression
and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The
DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable
CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the
Motorola Symphony™ DSP family, as shown in
Figure 1.
This design provides a two-fold performance
increase over Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct
memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal
100 MHz clock at 3.3 V.
2
16
12
5
Program RAM/
X Data
Instruction
RAM
Y Data
Cache
5632
×
24
RAM
3072
×
24
ROM
5632
×
24
Program ROM
6144
×
24
ROM
30K
×
24
6144
×
24
Bootstrap ROM
192
×
24
Triple
Timer
DAX
(SPDIF)
Host
Interface
ESAI
SHI
Memory
Expansion
Area
PIO_EB
PM_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
DRAM/SRAM
Bus
11
Interface
&
I - Cache Control
Control
Internal
Data
Bus
Switch
EXTAL
External
Data Bus
Switch
24
Data
Clock
Generator
PLL
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
CLKOUT
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Mngmnt.
6
JTAG
OnCE
RESET
PINIT/NMI
AA0456G
Figure 1 DSP56362 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
IMOTOROLA
DSP56362 Advance Information
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MOTOROLA
DSP56362 Advance Information
iii
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Freescale Semiconductor, Inc.
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
IBIS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-I
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FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Note:
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage*
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
*Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
!!
DSP56362 Advance Information
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MOTOROLA
Freescale Semiconductor, Inc.
OVERVIEW
FEATURES
•
Multimode, multichannel decoder software functionality
–
–
–
Dolby Digital and Pro Logic
MPEG2 5.1
DTS
Bass management
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–
•
Digital audio post-processing capabilities
–
–
–
–
3D Virtual surround sound
Lucasfilm THX5.1
Soundfield processing
Equalization
•
Digital Signal Processing Core
–
–
–
–
100 MIPS with a 100 MHz clock at 3.3 V +/- 5%
Object code compatible with the DSP56000 core
Highly parallel instruction set
Data arithmetic logic unit (ALU)
•
•
•
•
–
•
•
•
•
•
•
–
•
•
Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
Position independent code (PIC) support
Addressing modes optimized for DSP applications (including immediate offsets)
On-chip instruction cache controller
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
Six DMA channels supporting internal and external accesses
One-, two-, and three- dimensional transfers (including circular buffering)
Program control unit (PCU)
Direct memory access (DMA)
MOTOROLA
DSP56362 Advance Information
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