TC55V4000ST-70,-85
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55V4000ST is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 0.5
µA
standby
current (at V
DD
=
3 V, Ta
=
25°C) when chip enable ( CE ) is asserted high. There are two control inputs. CE is
used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This
device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. The TC55V4000ST is available in a normal pinout plastic 32-pin thin-small-outline package
(TSOP).
FEATURES
•
•
•
•
•
•
Low-power dissipation
Operating: 10.8 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Standby Current (maximum):
3.6 V
3.0 V
7
µA
5
µA
•
Access Times (maximum):
TC55V4000ST
-70
Access Time
CE
Access Time
OE
Access Time
-85
85 ns
85 ns
45 ns
70 ns
70 ns
35 ns
•
Package:
TSOPⅠ32-P-0.50 (ST)
(Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
32 PIN TSOP
16
1
PIN NAMES
A0~A18
R/W
OE
CE
Address Inputs
Read/Write Control
Output Enable
Chip Enable
Data Inputs/Outputs
Power
Ground
I/O1~I/O8
V
DD
GND
17
32
(Normal pinout)
Pin No.
Pin Name
Pin No.
Pin Name
1
A11
17
A3
2
A9
18
A2
3
A8
19
A1
4
A13
20
A0
5
R/W
21
I/O1
6
A17
22
I/O2
7
A15
23
I/O3
8
V
DD
24
GND
9
A18
25
I/O4
10
A16
26
I/O5
11
A14
27
I/O6
12
A12
28
I/O7
13
A7
29
I/O8
14
A6
30
CE
15
A5
31
A10
16
A4
42
OE
2001-11-30
1/10
TC55V4000ST-70,-85
BLOCK DIAGRAM
CE
A13
A17
A15
A18
A16
A14
A4
A5
A6
A7
A12
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
ROW ADDRESS
DECODER
V
DD
GND
MEMORY CELL ARRAY
2,048
×
256
×
8
(4,194,304)
8
DATA
CONTROL
SENSE AMP
COLUMN ADDRESS
DECODER
CLOCK
GENERATOR
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A3 A2 A1 A0 A8 A9 A11 A10
OE
R/W
CE
CE
OPERATING MODE
MODE
Read
Write
Output Deselect
Standby
*
= don't care
H = logic high
L = logic low
CE
OE
R/W
H
L
H
*
Output
Input
High-Z
High-Z
I/O1~I/O8
POWER
I
DDO
I
DDO
I
DDO
I
DDS
L
L
L
H
L
*
H
*
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
VALUE
−0.3~4.6
−0.3*~4.6
−0.5~V
DD
+
0.5
0.6
260
−55~150
−40~85
UNIT
V
V
V
W
°C
°C
°C
*:
−3.0
V when measured at a pulse width of 50ns
2001-11-30
2/10
TC55V4000ST-70,-85
DC RECOMMENDED OPERATING CONDITIONS
(Ta
= −
40° to 85°C)
2.3 V~3.6 V
SYMBOL
PARAMETER
MIN
V
DD
V
IH
V
IL
V
DH
*:
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
2.3
2.2
−0.3*
1.5
TYP
3.0
MAX
3.6
V
DD
+
0.3
V
DD
×
0.22
3.6
V
V
V
V
UNIT
−3.0
V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (
Ta
= −
40° to 85°C
, V
DD
=
2.3 to 3.6 V)
SYMBOL
I
IL
I
OH
I
OL
I
LO
PARAMETER
Input Leakage
Current
Output High Current
Output Low Current
Output Leakage
Current
V
IN
=
0 V~V
DD
V
OH
=
V
DD
−
0.5 V
V
OL
=
0.4 V
CE
=
V
IH
or
OE
=
V
IH
or R/W
=
V
IL
, V
OUT
=
0 V~V
DD
CE
=
V
IL
and R/W
=
V
IH
,
I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
TEST CONDITION
MIN
−0.5
2.1
min
1
µs
t
cycle
min
1
µs
TYP
0.05
MAX UNIT
±1.0
±1.0
50
mA
10
45
mA
5
3
0.6
6
0.7
7
0.5
1
5
µA
mA
µA
mA
mA
µA
l
DDO1
Operating Current
l
DDO2
CE
=
0.2 V and
R/W
=
V
DD
−
0.2 V,
I
OUT
=
0 mA,
Other Input
=
V
DD
−
0.2 V/0.2 V
CE
=
V
IH
V
DD
=
3.0 V
±
10%
l
DDS1
V
DD
=
3.0 V
±
10%
V
DD
=
3.3 V
±
0.3 V
Ta
=
25°C
Ta
= −40~85°C
Ta
=
25°C
Ta
= −40~85°C
Ta
=
25°C
Standby Current
l
DDS2
CE
=
V
DD
−
0.2 V,
V
DD
=
1.5 V~3.6 V
V
DD
=
3 V
Ta
= −40~40°C
Ta
= −40~85°C
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
Note:
PARAMETER
Input Capacitance
Output Capacitance
V
IN
=
GND
V
OUT
=
GND
TEST CONDITION
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
2001-11-30
3/10
TC55V4000ST-70,-85
(Ta
= −
40° to 85°C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
TC55V4000ST
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
70
5
0
10
-70
MAX
70
70
35
30
30
MIN
85
5
0
10
-85
MAX
85
85
45
35
35
ns
UNIT
AC CHARACTERISTICS AND OPERATING CONDITIONS
WRITE CYCLE
TC55V4000ST
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
70
50
60
0
0
0
30
0
-70
MAX
25
MIN
85
55
70
0
0
0
35
0
-85
MAX
35
ns
UNIT
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
30 pF
+
1 TTL Gate
0.4 V, 2.4 V
V
DD
×
0.5
V
DD
×
0.5
5 ns
2001-11-30
4/10
TC55V4000ST-70,-85
(Ta
= −
40° to 85°C, V
DD
=
2.3 to 3.6 V)
READ CYCLE
TC55V4000ST
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
85
5
0
10
-70
MAX
85
85
45
35
35
MIN
100
5
0
10
-85
MAX
100
100
50
40
40
ns
UNIT
AC CHARACTERISTICS AND OPERATING CONDITIONS
WRITE CYCLE
TC55V4000ST
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
85
55
70
0
0
0
40
0
-70
MAX
35
MIN
100
60
80
0
0
0
40
0
-85
MAX
40
ns
UNIT
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
30 pF
+
1 TTL Gate
V
DD
−
0.2 V, 0.2 V
V
DD
×
0.5
V
DD
×
0.5
5 ns
2001-11-30
5/10
京公网安备 11010802033920号
EEWORLD
