CAT24AA01, CAT24AA02
1-Kb and 2-Kb I
2
C CMOS
Serial EEPROM
Description
The CAT24AA01/24AA02 are 1−Kb and 2−Kb CMOS Serial
EEPROM devices internally organized as 128x8/256x8 bits.
They feature a 16−byte page write buffer and support both the
Standard (100 kHz) and the Fast (400 kHz) I
2
C protocols.
In contrast to the CAT24C01/24C02, the CAT24AA01/24AA02
have no external address pins, and are therefore suitable in
applications that require a single CAT24AA01/02 on the I
2
C bus.
Features
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Supports Standard and Fast I
2
C Protocol
1.7 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
CC
SOIC−8
W SUFFIX
CASE 751BD
TSOT−23
TB SUFFIX
CASE 419AE
PIN CONFIGURATIONS
SOIC
NC
NC
NC
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
(Top View)
TSOT−23
SCL
1
2
3
4
V
CC
5
WP
SCL
CAT24AA01
CAT24AA02
WP
SDA
V
SS
SDA
(Top View)
PIN FUNCTION
V
SS
Figure 1. Functional Symbol
Pin Name
SDA
SCL
WP
V
CC
V
SS
NC
Function
Serial Data/Address
Clock Input
Write Protect
Power Supply
Ground
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
August, 2009
−
Rev. 3
1
Publication Order Number:
CAT24AA01/D
CAT24AA01, CAT24AA02
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. REABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode @ 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
(
V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to 85°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write
All I/O Pins at GND or V
CC
Pin at GND or V
CC
−0.5
V
CC
x 0.7
Min
Max
0.5
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
mA
mA
mA
mA
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to 85°C, unless otherwise specified.)
Symbol
C
IN
(Note 2)
C
IN
(Note 2)
I
WP
(Note 4)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH
V
IN
> V
IH
Conditions
Max
8
6
100
1
Units
pF
pF
mA
4. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
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CAT24AA01, CAT24AA02
Table 5. A.C. CHARACTERISTICS
(Note 5) (V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to 85°C, unless otherwise specified.)
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
(Note 6)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 6)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 6, 7)
5.
6.
7.
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
ms
ms
ms
ms
ns
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3 mA (V
CC
≥
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
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CAT24AA01, CAT24AA02
Power−On Reset (POR)
Each CAT24AA01/02 incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after V
CC
exceeds the POR trigger level
and will power down into Reset mode when V
CC
drops
below the POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
Pin Description
SCL:
The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA:
The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and delivered on the negative
edge of SCL.
WP:
When the Write Protect input pin is forced HIGH by an
external source, all write operations are inhibited. When the
pin is not driven by an external source, it is pulled LOW
internally.
Functional Description
The CAT24AA01/02 supports the Inter−Integrated
Circuit (I
2
C) Bus protocol. The protocol relies on the use of
a Master device, which provides the clock and directs bus
traffic, and Slave devices which execute requests. The
CAT24AA01/02 operates as a Slave device. Both Master
and Slave can transmit or receive, but only the Master can
assign those roles.
I
2
C BUS PROTOCOL
The 2−wire I
2
C bus consists of two lines, SCL and SDA,
connected to the V
CC
supply via pull−up resistors. The
Master provides the clock to the SCL line, and the Master
and Slaves drive the SDA line. A ‘0’ is transmitted by
pulling a line LOW and a ‘1’ by releasing it HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). A START is generated by a
HIGH to LOW transition, while a STOP is generated by a
LOW to HIGH transition. The START acts like a wake−up
call. Absent a START, no Slave will respond to the Master.
The STOP completes all commands.
START/STOP Condition
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The four most significant bits of the Slave
address are 1010 (Ah).
For the CAT24AA01/02 the next three bits must be 000.
The last bit, R/W, instructs the Slave to either provide (1)
or accept (0) data, i.e. it signals a Read (1) or a Write (0)
request.
Acknowledge
During the 9
th
clock cycle following every byte sent onto
the bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
0
0
0
R/W
Figure 3. Slave Address Bits
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CAT24AA01, CAT24AA02
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t
AA
)
ACK SETUP (≥ t
SU:DAT
)
Figure 4. Acknowledge Timing
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
HD:STA
t
HIGH
t
LOW
t
R
t
HD:DAT
t
SU:DAT
t
SU:STO
t
DH
t
BUF
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 5). The STOP
starts the internal Write cycle, and while this operation is in
progress (t
WR
), the SDA output is tri−stated and the Slave
does not acknowledge the Master (Figure 6).
Page Write
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (t
WR
) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 7). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (t
WR
).
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating
or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1
st
data byte
(Figure 8). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24AA01/02 is shipped erased, i.e., all bytes are FFh.
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