PT2259
Volume Controller IC
DESCRIPTION
PT2259 is an 8-pin 2-channel volume controller which
utilizes CMOS technology and incorporates the I
2
C
interface control. The controller features an
attenuation range of 0 to -79dB, low noise output, a
high degree of stereo separation and requires only a
small number of external components. PT2259 is an
essential component for modern audio visual systems.
FEATURES
•
•
•
•
•
•
•
•
Attenuation range: 0 to -79dB in 1dB steps
Operating voltage: 4 to 10V
Low power consumption
Low signal noise: S/N > 100dB (A-weighting)
Stereo separation > 100dB
Requires few external components
2-channel volume individual adjust
Available in 8 Pins DIP or SOP
APPLICATIONS
•
•
•
•
•
Audio/visual surround sound systems
Car audio systems
Mini-compo systems
Computer multi-media speakers
Other audio applications
BLOCK DIAGRAM
Tel: 886-66296288
‧
Fax: 886-29174598
‧
http://www.princeton.com.tw
‧
2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT2259
APPLICATION CIRCUIT
IMPROVE VDD NOISES REJECTION
LIN
C1
10uF
1 LIN
RIN 8
ROUT 7
VDD 6
SCL 5
C2
10uF
C4
10uF
RIN
LIN
C1
10uF
1 LIN
RIN 8
ROUT 7
VDD 6
SCL 5
C2
10uF
C4
10uF
RIN
LOUT
C3
10uF
2 LOUT
3 VSS
4 SDA
ROUT
R1
C5
100uF
C6
0.1uF
100
VDD
LOUT
C3
10uF
2 LOUT
3 VSS
4 SDA
ROUT
VREG
VDD
PT2259
PT2259
C5
100uF
C6
0.1uF
MCU
MCU
ADD a RC filter on the VDD path
Use a regulated supply
IMPROVE INPUT ESD HANDLING CAPABILITY
P T2259
AUDIO IN
10uF
2K
IN
BAV99
VDD
P T2259
VDD
AUDIO IN
33K
10uF
IN
2K
33K
VREF
VREF
ADD a Resistor on the input path
ADD a protection diode on the input path
V1.3
2
July, 2009
PT2259
ORDERING INFORMATION
Valid Part Number
PT2259
PT2259-S
Package Type
8 Pins, DIP, 300mil
8 Pins, SOP, 150mil
Top Code
PT2259
PT2259-S
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name
LIN
LOUT
VSS
SDA
SCL
VDD
ROUT
RIN
I/O
I
O
-
I
I
-
O
I
Description
Left Channel Input
(capacitor coupled to input port)
Left Channel Output
(capacitor coupled to output port)
Ground
2
I C Data Input
I
2
C Clock Input
Power Supply
Right Channel Output
(capacitor coupled to input port)
Right Input Channel
(capacitor coupled to output port)
Pin No.
1
2
3
4
5
6
7
8
V1.3
3
July, 2009
PT2259
FUNCTIONAL DESCRIPTION
I
2
C BUS INTERFACE
In PT2259 the DATA and CLK make up the bus interface through which data is transmitted to and from the
microprocessor.
DATA VALIDITY
Data on the DATA line is considered valid and stable only when the CLK signal is in the “high” state. In addition, the
“high” and “low” states of the DATA line can change only when the CLK signal is in the “low” state. Please refer to the
diagram below:
START AND STOP CONDITIONS
A start condition is activated when:
1. the CLK signal is set to “high”, and
2. the DATA signal shifts from “high” to “low”
A stop condition is activated when:
1. the CLK signal is set to “high”, and
2. the DATA signal shifts from “low” to “high”
Please refer to the timing diagram below:
V1.3
4
July, 2009
PT2259
BYTE FORMAT
Every byte transmitted to the DATA line consists of 8 bits and each byte must be followed by an “acknowledge” bit. The
MSB is transmitted first.
ACKNOWLEDGE SIGNAL
During the ninth clock pulse, the microprocessor puts a resistive “high” level on the DATA line. If the peripheral audio
processor (PT2259) acknowledges, it will pull the DATA line from a “high” state to a “low” state during this acknowledge
clock phase so that the DATA line is in a stable “low” state during this clock pulse. Please refer to the diagram below.
The audio processor that has been address (PT2259) must generate an “acknowledge” signal after receiving each byte
or the DATA line will remain at the “high” level during the ninth clock pulse.
TRANSMISSION WITHOUT ACKNOWLEDGE
If you do not wish the audio processor (PT2259) to detect the “acknowledge” signal, a simpler microprocessor
transmission method can be used: after PT2259 has received a byte wait for one clock pulse and do not acknowledge it.
If this approach is used, however, there is a greater chance for faulty operations to occur and noise immunity will be
decreased.
I
2
C START TIME
When PT2259 is powered on, a short period must elapse before voltage becomes stable. After the power is turned on,
PT2259 must wait at least 200ms before it is able to send an I
2
C control signal otherwise control efficacy and normal
operation will be comprised. Please refer to the diagram below:
V1.3
5
July, 2009
京公网安备 11010802033920号
EEWORLD
