D A T A S H E E T
Imaging
Imaging Product Line
RA1133J Full Frame CCD Image Sensor
24 µm square pitch, 1100 x 330 pixel configuration
Description
The RA1133J is a full frame CCD
sensor with reset capabilities designed
specifically for use in spectroscopy,
biomedical imaging and related scientific
imaging applications. The package for
the array is designed with an integrated
two stage thermoelectric cooler. This
enables the device to be run 40° C
below ambient temperature, -15° C
when compared to room temperature.
Its combination of very low noise and
low dark current make it ideal for low
light, high dynamic range and high
resolution applications.
MPP Operation
A major source of dark current in
devices such as this originates in
surface states at the Si-SiO2 interface.
A unigue design and process enables
the RA1133J to be run in "multi-pinned
phase" or MPP mode of operation.
This helps eliminate dark current
generation in the interface surface
states. By holding the vertical clocks
at negative potential during integration
and horizontal signal readout, the
surface will not be depleted and the
surface state will not generate dark
current.
Features
•
363,000 picture elements (pixels) in
a 1100 x 330 configuration
•
24 µm square pixels
•
2-phase buried channel process
•
On-chip amplifier for low noise and
high speed readout
•
Dynamic range greater than 25,000:1
•
On-chip temperature sensor
•
Two stage TE cooler integrated into
the package
•
Hermetically sealed
•
100% fill factor
•
10 MHz data rate
The imager is structured with a single
output register at one end of the imaging
columns. A lateral reset drain is located
adjacent to this readout register which
enables the dumping of accumulated
charge from the array. Two phase clocks
are needed to drive the readout register.
Three phase clocks are needed to drive
imaging cells. The array is available in
a 30-pin metal package with an integrated
TE cooler as shown in Figure 1. Package
dimensions are shown in Figure 8.
Caution: While the RA1133J imagers have been
designed to resist electrostatic discharge (ESD),
they can be damaged from such discharges.
Always observe proper ESD precautions when
handling and storing these sensors.
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DSP-303.01C- 8/2002W Page 1
Full Frame CCD Sensor
Imaging Area
The imaging area is an array of 1100
columns (vertical CCD shift registers).
Each column has 330 picture elements.
The pixel size is 24 µm by 24 µm. The
total imaging area is 26.4 mm by 7.92 mm.
Typical spectral response as a function
of wavelength is shown in Figure 2.
This is for both the standard array and
an array coated with lumogen, an UV
phosphor that extends the range of the
detector into the ultraviolet.
In the vertical direction, each pixel
corresponds to one stage (three electrodes)
of the shift register. The three electrode
groups are driven by three-phases (Ø1V -
Ø3V) brought in from both edges of the
array to improve clock electrode response
time. Charge packets (imaging data) in the
vertical register can be shifted to the hori-
zontal readout by clocking the three phases
(Ø1V, Ø2V and Ø3V). A transfer gate (ØTG) is
provided at the interface of the vertical reg-
ister. The transfer gate controls the transferring
of charge into the horizontal readout register.
Charge flow is from Ø3 gate of the vertical
shift register into Ø1 gate of the horizontal
readout register. The control function is
performed by pulsing the transfer gate high
to permit the charge flow from the vertical
register into the horizontal register for
readout. When the potential of the vertical
register electrodes is held steady, a potential
well is created beneath the storage gates
Ø1V and Ø2V. When an image impinges
on the sensing area, an electrical signal of
the scene will be collected in the potential
well during this integration period.
Following the integration interval, the
collected charge (signal) in the array can
be read out as a full frame image by
transferring the charge, one or more rows at
a time, into the horizontal shift register.
From here, the charge can be shifted serially
to the output amplifier. A mechanical
shutter is needed to shield the array from
incident light during the readout process.
A strobe illumination could be used to
stimulate the shuttered mode of operation.
Image smearing degrades the performance,
particularly at low data rates, unless
shuttering is provided.
Figure 1. Pinout Configuration
+
Ø1V
Ø3V
ØTG2
VLD
ØLG2
LS
TEMP+
TEMP-
VSUB
ØTG2
Ø3V
Ø1V
Ø2V
ØTG1
ØSG
-
Ø2V
ØTG1
N/C
VSUB
LS
Ø1H
Ø2H
ØLG1
VDD
VOUT
VLD
VSS
VRD
ØRG
VOG
Figure 2. Quantum Efficiency
Quantum Efficiency (%)
60
50
40
30
20
10
0
200
300
400
500
600
700
800
900
1000
1100
Wavelength, nm
Figure 3. Functional Diagram
Ø1V
Ø2V
Ø3V
ØTG
Imaging Area
1100 (H) x 330 (V) - active pixels
Horizontal Register
The horizontal shift register is driven by
two phase clocks (Ø1H and Ø2H). The
horizontal register has 1100 stages plus
an extension of 35 stages ( 3 dummy stages,
16 leading isolation stages and 16 trailing
isolation stages). As a result, amplifier
power is dissipated more efficiently and
dark current generation by localized heating
is minimized.
Ø1H
Ø2H
ØLG
VLD
Horizontal CCD Shift
Output Buffer
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DSP-303.01C - 8/2002W Page 2
Full Frame CCD Sensor
Summing Mode
At the end of the horizontal register, there is
an ouput summing well which can be clocked
to allow multiple-pixel summation of the
scene. This summing well is located after
the 19 extra stages of the horizontal register
and prior to the DC biased gate (VOG) as
shown in Figure 5. The summing gate (ØSG)
can be clocked with one of the horizontal
clock phases or with its own clock generator
(see Figure 4a for summing gate timing). For
example, two parallel lines of charge are
additively transferred into the serial register,
then the summing gate is pulsed low after
the charge from two serial pixels has been
transferred into the summing well. Thus,
the resulting signal represents the sum of
charges in four (2x2) contiguous pixels from
the imaging region. It effectively reduces
the 1100 x 330 device to a 550 x 165 array
and increases the pixel size by four times.
Other variations of this technique can be
useful for low-light level situations, i.e.,
scenes with low contrast or a low signal-to-
noise ratio. There is, of course, a loss in
resolution that accompanies the gain in
effective pixel size.
Figure 4C. Horizontal CCD Shift Register Timing
Normal Mode
t1
t2
t3
t4
t5
t6
t7
t8
H1
1V
2V
3V
TG
MPP Mode
t9
t10
t11
t12
t13
t14
t15
H1
1V
2V
Table
3V
TG
Table 2. Vertical Timing Diagram Characteristics
Item
Sym
Min
Typ
Max
Units
Output Amplifier
There is an on-chip amplifier that is
located at the end of the extended shift
register. The amplifier is a two stage
buried channel transistor amplifier as
shown in Figure 5. It is designed to operate
with data rates in excess of 10 MHz. It
has a bandwidth of approximately 60 MHz
with a 10 pF load.
Temperature Monitoring
The RA1133J device has a temperature
sensor integrated into the package for
monitoring array temperature.
FE H1 to FE 1V
FE 1V to RE 3V
RE 3V to FE 2V
FE 2V to RE 1V
RE 1V to FE 3V
FE 3V to RE 2V
RE 2V to FE TG
FE TG to RE H1
FE H1 to RE 2V
RE 2V to RE 3V
RE 3V to FE 2V
FE 2V to RE 1V
RE 1V to FE 3V
FE 3V to FE TG
FE TG to RE H1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t14
2.6
2.6
2.6
5.2
1.4
1.4
4.6
2.6
2.6
5.2
2.6
2.6
2.8
4.6
2.6
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Figure 4a. Horizontal CCD Shift Register Timing
t1
t2
Timing Requirements
The timing recommended to run the RA1133J
imager in the low speed and low noise mode of
operation is shown in Figures 4A, 4B, and 4C. A
50% duty cycyle, two phase clock will drive the
horizontal register to its highest speed. Figure 4a
shows the timing of the horizontal two phase
clocks, summing well clock and reset clock. To
achieve high charge transfer, serial clocks must
cross between 10% and 90% of the peak voltage.
In addition, the rise and fall times of the two
phase clocks need to be more than 50 ns in order
to prevent the injection of spurious charge into
the CCD channel.
Ø1H
Ø2H
t3
t4
t9
ØSG
t5
t6
t7
ØRS
t8
Video
Output
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DSP-303.01C - 8/2002W Page 3
Full Frame CCD Sensor
Timing Requirements
(cont.)
The timing shown in Figure 4a is
repeated 1100 + 35 (or more) times
to allow the readout of one complete
line of the image.
Figure 4b shows the timing require-
ments for the vertical register. Over-
lapping of the vertical clocks are
normally longer than 5 µs. Rise and
fall times of all clocks need to be 3 µs
or longer in order to prevent spurious
charge into the CCD channel. All
vertical clock transitions should occur
when the horizontal clocks are held
steady.
Timing for MPP and normal mode is
shown. The difference between the
two modes is that during integration,
all clocks must be held low for MPP
mode.
potential which is more positive than the low state
channel potential of the transfer gate. Similar to a
lateral antiblooming drain, charge will spill prefer-
entially into the rapid discharge drain. Due to the
fixed potential barrier, the HCCD cannot be
completely cleared of charge and thus one horizontal
shift sequence is required before resumption of valid
data read.
Table 1. Timing Diagram Characteristics
Item
Sym
T1
T2
T3
T4
T5
T6
T7
T8
T9
10
100
+0
+0
50
+0
Min
Typ
50
100
Max
Units
ns
ns
ns
ø
1, 2H
rise/fall time
ø
1, 2H
clock period
ø
SG
delay from
ø
H2
edge
ø
SG
rise/fall time
ø
RG
delay from
ø
SG
edge
ø
SG
delay from
ø
RG
edge
ø
RG
rise/fall time
ø
RG
pulse duration
ø
SG
pulse duration
50
ns
ns
ns
ns
ns
ns
Array Cooling
Both the dark current and the noise
performance of the array can be im-
proved by cooling. The dark current
will be reduced by 50% for approx-
imately every 6 - 8 ° C reduction in
array temperature. Cooling can be
achieved via the integrated thermo-
electric cooler. The bias supplies TEC+
and TEC- electronically control this
cooler. This is a two-stage cooler
capable of reducing the temperature
of the array 40° C from the ambient
temperature. Additional cooling can be
achieved by decreasing the ambient
temperature or by cooling the heat sink
on the TE cooler as shown in Figure 6
and Figure 7.
Figure 4b. Vertical CCD Shift Register Timing and Its Relationship to
Horizontal Clocks in Normal and MPP Mode
Quiescent
State of All
Horizontal
Phases
During ø C
Transitions
Horizontal
Clear Out 1
1135 (+) ø
Clock Cycles
1135 (+) ø
Clock Cycles
to read 1 line
Region of Interest
Rapid access to regions of interest is
facilitated by use of a lateral charge
drain. The drain is constructed adjacent
to the horizontal CCD (HCCD) shift register.
Unwanted lines of data are quickly dis-
posed without the requirement for hori-
zontal transfer. In this manner, entire lines
of image data can be disposed of by a single
vertical shift sequence, with a time penalty
of 20 µs. This is to be contrasted with the
normal read sequence which includes both
the vertical shift (20 µs), plus readout of
the 1130 horizontal elements (2260 µs).
As the unwanted lines are transferred from
storage region into the HCCD, the hori-
zontal phases are held high to maintain a
surface
ø1H
ø2H
ø1V
ø2V
ø3V
øTG
End
Integration
Period
Repeat 330(+) Times to
Read Out the Entire Image
Start
Integration
Period
Normal
Mode
ø1V
ø2V
ø3V
øTG
MPP
Mode
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DSP-303.01C - 8/2002 Page 4
Full Frame CCD Sensor
Figure 5. Output Structure
VRD
ØRG
VOG
ØSG
VDD
Ø1H
Two Stage Amplifier
VSUB
VOUT
VSS
VSS
Figure 6. TEC Current vs. Chip Temperature (Ambient Temperature)
Current to Thermo-Electric Cooler, Amp
.5
1.0
1.5
2.0
0
0
-10
-20
T
Chip
– T
Ambient
, C
2.5
2.3° C/W
Heat Sink
-30
-40
-50
-60
-70
-80
1.8C/W
Heat Sink
1.3 C/W
Heat Sink
.5 C/W
Heat Sink
0 C/W
Heat Sink
Figure 7. Heat Sink Temperature vs. Chip Temperature
Heat Sink Temperature
T
Hot
, C
10
0
I = .5A
TEC Current
-10
I = 1.1A
TEC Current
-20
I = 2.0A
TEC Current
-30
I = 2.5A
TEC Current
-40
20
30
40
50
60
Chip Temperature
T
CPLP
, C
-50
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DSP-303.01C - 8/2002 Page 5
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