DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
1. General Description
The DM9601 is a fully integrated and cost-effective
single chip USB to Fast Ethernet MAC controller with
10/100 PHY. It is designed with the low power and
high performance process. It is a 3.3V device with 5V
tolerance and it supports 3.3V and 5V signaling.
The DM9601 provides USB transceiver which is compliant
with USB1.1, 10/100M PHY, MAC controller, memory
controller and an external MII interface, to connect
HPNA device or other transceivers that support MII
interface. This chip already integrates into 16K byte
SRAM. The DM9601 has interfaces to the UTP3, 4, 5 in
10Base-T and UTP5 in 100Base-TX. It is fully compliant with
the IEEE 802.3u Spec. Its auto-negotiation function will
automatically configure the DM9601 to take the maximum
advantage of its abilities. The DM9601 also supports IEEE
802.3x full-duplex flow control.
The DM9601 supports 3 wake-up event to wake-up system
from suspend mode. There are 7 GPIO pins (General
purpose I/O) for user’s application.
2. Block Diagram
LED
External MII
Interface
EEPROM
Interface
PHYceiver
100 Base-TX
transceiver
TX+/-
10 Base-T
Tx/Rx
RX+/-
100 Base-TX
PCS
MII
MAC
TX Machine
EP / SIE
controller
DP
Control &Status
Registers
Memory
Management
USB
Tx/Rx
DM
RX Machine
Internal
SRAM
Autonegotiation
MII Management
Control
& MII Register
Final
Version: DM9601-DS-F01
June 22, 2002
1
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Table of Contents
1. General Description ..............................................1
2. Block Diagram………………………………………
1
10. Vendor Control and Status Register Set...........18
10.1 Network Control Register (00H)......................19
10.2 Network Status Register (01H) .......................19
10.3 TX Control Register (02H) ..............................20
10.4 TX Status Register I (03H)..............................20
10.5 TX Status Register II (04H).............................21
10.6 RX Control Register (05H) ..............................21
10.7 RX Status Register (06H) ...............................21
10.8 Receive Overflow Counter Register (07H) .....22
10.9 Back Pressure Threshold Register (08H) .......22
10.10 Flow Control Threshold Register (09H) ........22
10.11 RX/TX Flow Control Register (0AH) .............22
10.12 EEPROM & PHY Control Register (0BH) .....23
10.13 EEPROM & PHY Address Register (0CH) ...23
10.14 EEPROM & PHY Data
Register(EE_PHY_L:0DH EE_PHY_H:0EH) ..23
10.15 Wake Up Control Register (0FH)..................24
10.16 Physical Address Register (10H~15H) .........24
10.17 Multicast Address Register (16H~1DH)........24
10.18 General Purpose Control Register
(1EH)……….………………………………….….24
10.19 General Purpose Register (1FH) ..................25
10.20 TX SRAM Write Pointer Address Register
(20H~21H) .......................................................25
10.21 TX SRAM read Pointer Address Register
(22H~23H) .......................................................25
10.22 RX SRAM Write Pointer Address Register
(24H~25H) .......................................................25
10.23 RX SRAM Write Pointer Address Register
(26H~27H) .......................................................25
10.24 Vendor ID Register (28H~29H).....................26
10.25 Product ID Register (2AH~2BH) ...................26
10.26 Chip Revision Register (2CH).......................26
10.27 USB Device Address Register (F0H)............26
10.28 Receive Packet Counter Register (F1H) ......26
10.29 Transmit Packet Counter/USB Status Register
(F2H)................................................................26
10.30 USB Control Register (F4H) ........................27
10.31 EEPROM Format ……………………………..27
11. MII Register Description....................................28
11.1 Basic Mode Control Register (BMCR) – 00 ....29
11.2 Basic Mode Status Register (BMSR) – 01......30
Final
Version: DM9601-DS-F01
June 22, 2002
9.6 String0 Descriptor/Code array ..........................16
9.7 Descriptor of string1/2/3 are loaded from
EEPROM .........................................................17
3. Features ................................................................4
3.1 USB Characteristics............................................4
3.2 Tansceiver ..........................................................4
3.3 Other ...................................................................4
4. Pin Configuration ..................................................5
5. Pin Description......................................................6
5.1 MII Interface ........................................................6
5.2 EEPROM Interface .............................................6
5.3 USB Interface.......................................................... 6
5.4 Clock Interface ....................................................7
5.5 LED Interface ......................................................7
5.6 10/100 PHY/Fiber ...............................................7
5.7 Miscellaneous Pins .............................................7
5.8 Power Pins ..........................................................8
6. USB Standard Command .....................................9
6.1 Supported Standard Command ..........................9
6.2 Not Support Standard Commend .......................9
7. Vendor Command....................................................10
7.1 Register Type....................................................10
7.2 Memory Type ....................................................11
8. Interface 0 Configuration.....................................12
8.1 Endpoint 1 .........................................................12
8.2 Endpoint 2 .........................................................12
8.3 Endpoint 3 .........................................................12
9. Descriptor Values................................................13
9.1 Device Descriptor/18-Byte ................................13
9.2 Configuration0 Descriptor/8-Byte
........................14
9.3 Interface0 Descriptor/9-Byte .............................14
9.4 Endpoint1 Descriptor/6-Byte .............................15
9.5 Endpoint3 Descriptor/6-Byte .............................16
2
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
11.3 PHY ID Identifier Register #1 (PHYID1) – 02 .31
11.4 PHY Indentifier Register #2 (PHYID2)-03.......31
11.5 Auto-negotiation Advertisement Register
(ANAR)-04 .......................................................32
11.6 Auto-negotiation Link Partner Ability Register
(ANLPAR)-05...................................................33
11.7 Auto-negotiation Expansion Register (ANER) -
06 .....................................................................34
11.8 DAVICOM Specified Configuration Register
(DSCR)-16 .......................................................34
11.9 DAVICOM Specified Configuration and Status
Register (DSCSR) - 17 ....................................35
11.10 Base-T Configuration/Status (10BTCSR) - 18
.........................................................................37
12. Functional Description ......................................38
12.1 100Base-TX Operation ...................................38
12.1.1 4B5B Encoder..............................................38
12.1.2 Scrambler.....................................................38
12.1.3 Parallel to Serial Converter ..........................38
12.1.4 NRZ to NRZI Encoder..................................38
12.1.5 MLT-3 Converter..........................................38
12.1.6 MLT-Driver ...................................................38
12.1.7 4B5B Code Group Table 1 ..........................39
12.2 100Base-TX Receiver.....................................40
12.2.1 Signal Detect ...............................................40
12.2.2 Adaptive Equalization ..................................40
12.2.3 MLT-3 to NRZI Decoder...............................40
12.2.4 Clock Recovery Module ...............................40
12.2.5 NRZI to NRZ ................................................40
12.2.6 Serial to Parallel ..........................................40
12.2.7 Descrambler.................................................40
12.2.8 Code Group Alignment ................................41
12.2.9 4B5B Decoder..............................................41
12.3 10Base-T Operation........................................41
12.4 Collision Detection ..........................................41
12.5 Carrier Sense..................................................41
12.6 Auto-Negotiation .............................................41
12.7 Power Reduced Mode ....................................42
12.8 Power Down Mode..........................................42
12.9 Reduced Transmit Power Mode .....................42
13. DC and AC Electrical Characteristics ...............43
13.1 Absolute Maximum Rating (25∘C) ................43
13.2 Operating Conditions ......................................43
13.3 DC Electrical Characteristics ..........................44
13.4 USB Transceiver Interface DC Specification ..44
13.5 AC Electrical Characteristics & Timing
Waveforms.......................................................45
13.5.1 TP Interface .................................................45
13.5.2 Oscillator/ Crystal Timing.............................45
13.5.3 USB Transceiver Interface AC Specification45
13.5.4 External MII Interface Transmit Timing........45
13.5.5 External MII Interface Receive Timing.........46
13.5.6 MII Management Interface Timing ...............46
13.5.7 EEPROM Interface Timing ..........................47
14. Application Notes ..............................................48
14.1 Network Interface Signal Routing ...................48
14.2 10Base-T/100Base-TX Application Figure 14-1
.........................................................................48
14.3 10Base-T/100Base-TX (Power Reduction
Application) Figure 14-2................................49
14.4 USB1.1 Application Figure 14-3 ....................50
14.5 Power Decoupling Capacitors Figure 14-4 .....51
14.6 Ground Plane Layout Figure 11-5 ..................52
14.7 Power Plane Partitioning Figure 11-6 .............53
14.8 Magnetics Selection Guide Table 2 ................54
14.9 Crystal Selection Guide Figure 11-7...............54
15. Package Information .........................................55
15.1 LQFP 100L Outline Dimensions .....................55
16. Order Information..............................................56
Final
Version: DM9601-DS-F01
June 22, 2002
3
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
3. Features
3.1 USB Characteristics
■
■
■
3.3 Other
■
■
USB Specification revision 1.1 compliant
Supports 12MHz Full-Speed operation
Supports suspend mode and remote wake up
resume
Supports large internal 16K byte SRAM
Supports automatically load vendor ID and product
ID from EEPROM
Supports MII and the reverse MII interface
IEEE802.3x flow control for full-duplex mode
Back Pressure Mode for half-duplex mode flow
control
Supports wakeup frame, link status change and
Magic packet events for remote wake-up
Low-Power, Single-Supply 3.3V CMOS technology
Very Low Power Consumption mode
–Power
Reduced mode(cable detection)
–Power
Down mode
–Selectable
TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
■
■
■
■
■
■
■
Supports USB standard commands
Supports vendor specific commands
Supports test-mode for memory test.
Efficient TX/RX FIFO auto management.
■
3.2 Transceiver
■
■
■
■
10/100M PHY
USB 1.1
■
■
Compatible with 3.3V and 5.0V tolerant I/O
100-pin LQFP
4
Final
Version: DM9601-DS-F01
June 22, 2002
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
4. Pin Configuration: 100 Pin LQFP & with MII Interface Mode
AGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
GPIO4
GPIO5
GPIO6
NC
NC
NC
NC
NC
DVDD
NC
NC
NC
NC
NC
NC
NC
NC
DGND
NC
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DP
DM
AVDD
DVDD
GPIO3
GPIO2
GPIO1
GPIO0
EECS
EECK
EEDO
EEDI
DGND
LINKACT#
DUP#
SPEED#
CLK20MO
DGND
MDC
MDIO
DVDD
TX_EN
TXD3
TXD2
TXD1
DM9601
TXD0
TX_CLK
TEST5
RX_CLK
RX_ER
RX_DV
COL
CRS
DGND
RXD3
RXD2
RXD1
RXD0
LINK_I
DVDD
AVDD
TXO-
TXO+
AGND
AGND
RX-
RX+
AVDD
AVDD
BGRES
Final
Version: DM9601-DS-F01
June 22, 2002
NC
NC
NC
NC
DVDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
DGND
TEST1
TEST2
TEST3
TEST4
DVDD
X2_25M
X1_25M
DGND
SD
AGND
5
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