SPT7710
8-BIT, 150 MSPS, FLASH A/D CONVERTER
TECHNICAL DATA
AUGUST 17, 2001
FEATURES
• Metastable errors reduced to 1 LSB
• Low input capacitance: 10 pF
• Wide input bandwidth: 210 MHz
• 150 MSPS conversion rate
• Typical power dissipation: 2.2 watts
APPLICATIONS
• Digital oscilloscopes
• Transient capture
• Radar, EW, ECM
• Direct RF down-conversion
• Medical electronics: ultrasound, CAT instrumentation
GENERAL DESCRIPTION
The SPT7710 is a monolithic flash A/D converter capable
of digitizing a two volt analog input signal into 8-bit digital
words at a 150 MSPS (typ) update rate.
For most applications, no external sample-and-hold is re-
quired for accurate conversion due to the device’s narrow
aperture time, wide bandwidth, and low input capacitance.
A single standard –5.2 volt power supply is required for
operation of the SPT7710, with nominal power dissipation
of 2.2 W. A proprietary decoding scheme reduces meta-
stable errors to the 1 LSB level.
The SPT7710 is available in 42-lead ceramic sidebrazed
DIP, surface-mount 44-lead cerquad and 46-lead PGA
packages; the cerquad and PGA packages allow access
to additional reference ladder taps, an overrange bit, and a
data ready output. The SPT7710 is available in the indus-
trial temperature range.
BLOCK DIAGRAM
V
RTS
V
RTF
Analog Input
(Force or Sense) AGND DGND
V
EE
LINV
MINV
Preamp
256
Comparator
DRINV
MSB D7
DREAD
Clock
Buffer
255
V
R3
152
Overrange
151
D7 MSB
128
V
R2
127
D6
256 to
8-Bit
Encoder
D6
ECL
Latches
and
Buffers
D5
D4
64
D5
V
R1
63
D4
D3
2
D2
D1
D0 LSB
V
RBF
V
RBS
Convert
CLK
CLK
2
LSB D0
D1
D2
D3
These functions are
available in the PGA and
cerquad packages only.
1
Analog Input
(Sense or Force)
VEE
AGND
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
Negative Supply Voltage (V
EE
TO GND) –7.0 to +0.5 V
Ground Voltage Differential .................... –0.5 to +0.5 V
Input Voltage
Analog Input Voltage ............................... V
EE
to +0.5 V
Reference Input Voltage .......................... V
EE
to +0.5 V
Digital Input Voltage ................................ V
EE
to +0.5 V
Reference Current V
RTF
to V
RBF
........................ 25 mA
Output
Digital Output Current ............................... 0 to –30 mA
Temperature
Operating Temperature,ambient ............. –25 to +85 °C
junction ...................... +150 °C
Lead Temperature, (soldering 10 seconds) ..... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
=–5.2 V, R
Source
=50
Ω,
V
RBF
=–2.00 V, V
R2
=–1.00 V, V
RTF
=0.00 V, ƒ
CLK
=125 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
DC Accuracy
Integral Linearity Error
Differential Linearity Error
No missing codes
Analog Input
Offset Error V
RT
Offset Error V
RB
Input Voltage Range
Input Capacitance
Input Resistance
Input Current
Input Slew Rate
Large Signal Bandwidth
Small Signal Bandwidth
Clock Synchronous
Input Currents
Reference Input
Ladder Resistance
Reference Bandwidth
Timing Characteristics
Maximum Sample Rate
Clock to Data Delay
Output Delay Tempco
CLK-to-Data Ready Delay (t
D
)
Aperture Jitter
Acquisition Time
Dynamic Performance
Signal-to-Noise Ratio
Total Harmonic Distortion
Signal-to-Noise and Distortion
(SINAD)
TEST
CONDITIONS
ƒ
CLK
= 100 kHz
ƒ
CLK
= 100 kHz
TEST
LEVEL
VI
VI
MIN
SPT7710A
TYP
MAX
MIN
–0.95
–0.95
SPT7710B
TYP
MAX
±0.80
Guaranteed
+0.95
+0.95
UNITS
LSB
LSB
–0.75 ±0.60 +0.75
–0.75
+0.75
Guaranteed
–30
–30
–2.0
10
15
250
1,000
210
335
40
100
200
10
150
2.4
2
2.0
5
1.5
48
46
–52
–44
48
42
300
+30
+30
0.0
VI
VI
VI
Over full
input range
V
V
VI
V
V
V
V
VI
V
IV
V
V
V
V
V
ƒ
IN
= 3.58 MHz
ƒ
IN
= 50 MHz
ƒ
IN
= 3.58 MHz
ƒ
IN
= 50 MHz
ƒ
IN
= 3.58 MHz
ƒ
IN
= 50 MHz
VI
VI
VI
VI
VI
VI
–30
–30
–2.0
10
15
250
1,000
210
335
40
100
200
10
150
2.4
2
2.0
5
1.5
47
44
–50
–43
46
40
+30
+30
0.0
mV
mV
Volts
pF
kΩ
µA
V/µs
MHz
MHz
µA
500
500
V
IN
=F.S.
V
IN
=500 mV
P-P
300
Ω
MHz
MSPS
ns
ps/°C
ns
ps
ns
dB
dB
dB
dB
dB
dB
125
125
46
42
45
39
45
40
–48
–40
43
37
–46
–39
SPT7710
2
8/17/01
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
=–5.2 V, R
Source
=50
Ω,
V
RBF
=–2.00 V, V
R2
=–1.00 V, V
RTF
=0.00 V, ƒ
CLK
=125 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
Digital Inputs
Digital Input High Voltage
(MINV, LINV)
Digital Input Low Voltage
(MINV, LINV)
Clock Low Width, t
PWL
Clock High Width, t
PWH
Digital Outputs
Digital Output High Voltage
Digital Output Low Voltage
Power Supply Requirements
Supply Current
Power Dissipation
TEST
CONDITIONS
TEST
LEVEL
SPT7710A
MIN
TYP
MAX
SPT7710B
MIN
TYP
MAX
UNITS
VI
VI
VI
VI
50
Ω
to –2 V
50
Ω
to –2 V
+25 °C
+25 °C
VI
VI
VI
VI
–1.1
–2.0
4
4
–1.1
–0.7
–1.5
5
5
–1.1
–2.0
4
4
–1.1
–0.7
–1.5
5
5
Volts
Volts
ns
ns
Volts
Volts
mA
W
–1.5
425
2.2
550
2.9
425
2.2
–1.5
550
2.9
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all test are pulsed
tests; therefore, T
J
= T
C
= T
A
.
LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7710
3
8/17/01
TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
52
50
48
THD vs Input Frequency
52
50
48
46
44
S
= 125 MSPS
42
40
38
36
34
S
= 125 MSPS
46
44
42
40
38
36
34
1
10
100
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
1
10
100
Input Frequency (MHz)
Input Frequency (MHz)
SINAD vs Input Frequency
52
50
50
SNR, THD, SINAD vs Temperature
Signal-to-Noise and Distortion (dB)
SNR, THD, SINAD (dB)
48
46
44
42
40
38
36
34
S
= 125 MSPS
45
SNR
THD
40
SINAD
S
= 125 MSPS
IN
= 50 MHz
35
1
10
100
30
Input Frequency (MHz)
40
20
0
20
40
60
80
Temperature (°C)
SPT7710
4
8/17/01
Figure 1 – Typical Interface Circuit 1
L
*See below
+
U1
Voltage
Limiter
Analog Input
Can Be Either
Force Or Sense
V
IN
V
RTF
Preamp
Comparator
256
V
EE
2.2 µF
AGND
.01 µF
5.2 V
LINV
MINV
R
T
MSB D7
Clock
Buffer
255
D6
152
Typical Voltage Limiter
RS
49.9
D1
D2
151
D5
5.2
D1=D2=HP, 1N 5712
VR2
.01 µF
127
128
D4
256 To
8-Bit
Encoder
ECL
Latches
And
Buffers
D3
64
D2
63
V
EE
2
D1
VRef
2 V
10
2.2
+
U2
.01 µF
Q1 (1N2907A)
V
RBF
2.2 µF
.01 µF
1
LSB D0
Analog Input
Can Be Either
Force Or Sense
V
EE
V
IN
CLK
50
W
2
50
W
Convert
100116
50
W
50
W
CLK
.01 µF
2 V
(Analog)
AGND
.01 µF
V
EE
5.2 V
DGND
.01 µF
2 V (Digital)
GENERAL DESCRIPTION
The SPT7710 is a fast monolithic 8-bit parallel flash A/D
converter. The nominal conversion rate is 150 MSPS and
the analog bandwidth is in excess of 200 MHz. A major
advance over previous flash converters is the inclusion of
256 input preamplifiers between the reference ladder and
input comparators. (See block diagram.) This not only re-
duces clock transient kickback to the input and reference
ladder due to a low AC beta but also reduces the effect of
the dynamic state of the input signal on the latching char-
acteristics of the input comparators. The preamplifiers act
as buffers and stabilize the input capacitance so that it re-
mains constant for varying input voltages and frequencies
and, therefore, makes the part easier to drive than previ-
ous flash converters. The SPT7710 incorporates a propri-
etary decoding scheme that reduces metastable errors
(sparkle codes or
flyers)
to a maximum of 1 LSB.
The SPT7710 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. Every comparator also has a clock buffer
to reduce differential delays and to improve signal-to-
noise ratio. The output drive capability of the device can
provide full ECL swings into 50
Ω
loads.
TYPICAL INTERFACE CIRCUIT
The typical interface circuit is shown in figure 1. The
SPT7710 is relatively easy to apply depending on the
accuracy needed in the intended application. Wire-wrap
may be employed with careful point-to-point ground con-
nections if desired, but to achieve the best operation, a
SPT7710
5
8/17/01
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