[AK4372]
AK4372
DAC with built-in PLL & HP-AMP
GENERAL DESCRIPTION
The AK4372 is a 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is
synchronized to typical mobile phone clock frequencies. The AK4372 features an analog mixing circuit
that allows easy interfacing in mobile phone and portable communication designs. The integrated
headphone amplifier features “pop-noise free” power-on/off, a mute control, and it delivers 40mW of
power into 16Ω. The AK4372 is packaged in a 24-pin CSP (2.5mm×2.5mm) package, ideal for portable
applications.
FEATURE
Multi-bit
ΔΣ
DAC
Sampling Rate
- 8kHz ~ 48kHz
On chip perfect filtering 8 times FIR interpolator
- Passband: 20kHz
- Passband Ripple:
±0.02dB
- Stopband Attenuation: 54dB
Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
System Clock
- PLL Mode (MCKI): 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz,
14.4MHz, 13MHz, 12MHz and 11.2896MHz
- PLL Mode (BICK or LRCK): 64fs, 32fs or fs
- EXT Mode: 256fs/384fs/512fs/768fs/1024fs
- Input Level: AC Couple Input Available
Audio I/F Format: MSB First, 2’s Complement
- I
2
S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
- Master/Slave Mode
Digital Mixing: LR, LL, RR, (L+R)/2
Bass Boost Function
Digital ATT
Analog Mixing Circuit: 3 Inputs (Single-ended or Full-differential)
Stereo Lineout
- S/N: 90dB@3.3V
- Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step
Headphone Amplifier
- Output Power: 40mW x 2ch @16Ω, 3.3V
- S/N: 92dB@3.3V
- Pop Noise Free at Power-ON/OFF and Mute
- Output Volume: 0 ~ –63dB & +12/+6/0 dB Gain
1.5dB step (0 ~ –30dB), 3dB step (–30 ~ –63dB)
μ
P Interface: 3-wire/I
2
C
Power Supply: 1.6V
∼
3.6V
Power Supply Current: 3.8mA @1.8V (6.8mW, DAC+HP, No output)
AK4372ECB: Ta=
−
30
∼
85°C
AK4372VCB: Ta=
−
40
∼
85°C
Small Package: 24pin CSP (2.5mm x 2.5mm, 0.4mm pitch)
Register Compatible with AK4368
MS0684-E-02
-1-
2008/12
[AK4372]
■
Block Diagram
MCKO
MCKI
VCOC
LIN/IN−
MIN
AVDD
VSS1
BICK
LRCK
SDATA
DVDD
VSS2
Audio
Interface
PLL
VCOM
VCOM
DAC
Digital
Volume
Bass
Boost
De-
emphasis
Digital
Filter
(Lch)
LOUT
DAC
(Rch)
ROUT
PDN
I2C
CAD0/CSN
SCL/CCLK
SDA/CDTI
Serial I/F
HDP
Amp
MUTE
HPL
HDP
Amp
MUTE
HPR
RIN/IN+
MUTET
Figure 1. Block Diagram
MS0684-E-02
-2-
2008/12
[AK4372]
■
Ordering Guide
AK4372ECB
AK4372VCB
AKD4372
−30 ∼
+85°C
24pin CSP (0.4mm pitch)
−40 ∼
+85°C
24pin CSP (0.4mm pitch)
Evaluation board for AK4372
Black Type
Black Type
■
Pin Layout
5
4
3
2
1
A
B
C
D
E
Top View
5
VSS2
CCLK
CSN
PDN
MUTET
4
VCOC
MCKO
CDTI
LOUT
ROUT
3
MCKI
LRCK
DVDD
I2C
VCOM
2
BICK
LIN
HPR
AVDD
1
SDATA
RIN
MIN
HPL
VSS1
A
B
C
D
E
Top View
MS0684-E-02
-3-
2008/12
[AK4372]
■
Comparison with AK4370/71
1 Function
Function
Analog Mixing
PLL
Internal VREF
Hands-free Amp
Ta
Package
AK4370
2-Stereo
Single-ended Input
or Full-differential Input
No
No
No
−30 ∼
+85°C
24 pin QFN
(4mm x 4mm, 0.5mm pitch)
AK4371
3-Stereo
Single-ended Input
or Full-differential Input
Yes
Yes
Yes
−30 ∼
+85°C
32 pin QFN
(4mm x 4mm, 0.4mm pitch)
AK4372
1-Stereo + 1-Mono
Single-ended Input
or Full-differential Input
Yes
No
No
AK4372ECB:
−30 ∼
+85°C
AK4372VCB:
−40 ∼
+85°C
24 pin CSP
(2.5mm x 2.5mm, 0.4mm pitch)
2 Register (difference from AK4370/71)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
Reserved
Reserved
D7
PMVREF
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
RIN3HR
0
RIN3R
0
0
RIN3M
0
D6
D5
D4
D3
D2
PMPLL
PMLO
MUTEN PMHPR PMHPL
FS2
FS1
FS0
PLL3
PLL2
MCKAC
0
M/S
BF
PS0
MONO1 MONO0
BCKP
LRP
DIF2
DATTC LMUTE SMUTE
BST1
BST0
ATTL6
ATTL5
ATTL4
ATTL3
ATTL2
ATTR6
ATTR5
ATTR4
ATTR3
ATTR2
HPG0
MINHR MINHL
RINHR
LINHL
LOG
MINR
MINL
RINR
LINL
0
0
0
ATTS3
ATTS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RIN3HL LIN3HR LIN3HL RIN2HR RIN2HL
HPZ
HMUTE ATTH4
ATTH3
ATTH2
RIN3L
LIN3R
LIN3L
RIN2R
RIN2L
0
L3M
L3HM
L2M
L2HM
0
0
0
0
LDIFM
LIN3M
RIN2M
LIN2M
RIN1M
LIN1M
MMUTE
PMMO
MOG
ATTM3 ATTM2
These bits are changed from the AK4370/71.
These bits are deleted in the AK4372.
These bits are deleted in the AK4370.
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
0
0
0
LINHR
ATTH1
LINR
LM
LDIFH
DARM
ATTM1
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
0
0
0
RINHL
ATTH0
RINL
LHM
LDIF
DALM
ATTM0
MS0684-E-02
-4-
2008/12
[AK4372]
PIN/FUNCTION
No.
A1
B2
B3
A3
C3
Pin Name
SDATA
BICK
LRCK
MCKI
DVDD
I/O
I
I/O
I/O
I
-
Function
Audio Serial Data Input Pin
Audio Serial Data Clock Pin
Input / Output Channel Clock Pin
External Master Clock Input Pin
Digital Power Supply Pin, 1.6
∼
3.6V
Output for Loop Filter of PLL Circuit
A4 VCOC
O
This pin must be connected to VSS2 with one resistor and one capacitor in series.
A5 VSS2
-
Ground 2 Pin. Connected to VSS1.
B4 MCKO
O
Master Clock Output Pin
SDA
I/O Control Data Input/Output Pin (I2C mode : I2C pin = “H”)
C4
CDTI
I
Control Data Input Pin (3-wire serial mode : I2C pin = “L”)
SCL
I
Control Data Clock Pin (I2C mode : I2C pin = “H”)
B5
CCLK
I
Control Data Clock Pin (3-wire serial mode : I2C pin = “L”)
CAD0
I
Chip Address 0 Select Pin (I2C mode : I2C pin = “H”)
C5
CSN
I
Chip Select Pin (3-wire serial mode : I2C pin = “L”)
Power-down & Reset
D5 PDN
I
When “L”, the AK4372 is in power-down mode and is held in reset.
The AK4372 must be reset once upon power-up.
Control Mode Select Pin
D3 I2C
I
“H”: I
2
C Bus, “L”: 3-wire Serial
Mute Time Constant Control pin
E5 MUTET
O
Connected to the VSS1 pin with a capacitor for mute time constant.
D4 LOUT
O
Lch Stereo Line Output Pin
E4 ROUT
O
Rch Stereo Line Output Pin
Common Voltage Output Pin
E3 VCOM
O
Normally connected to the VSS1 pin with a 2.2μF electrolytic capacitor.
E2 AVDD
-
Analog & PLL Power Supply Pin, 1.6
∼
3.6V
E1 VSS1
-
Ground 1 Pin
D2 HPR
O
Rch Headphone Amp Output
D1 HPL
O
Lch Headphone Amp Output
C1 MIN
I
Mono Analog Input Pin
I
Rch Analog Input Pin (LDIF bit =“0” : Single-ended Input)
RIN
B1
IN+
I
Positive Line Input Pin (LDIF bit =“1” : Full-differential Input)
LIN
I
Rch Analog Input Pin (LDIF bit =“0” : Single-ended Input)
C2
I
Negative Line Input Pin (LDIF bit =“1” : Full-differential Input )
IN−
Note 1. All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not
be left floating. The MCKI pin can be left floating only when the PDN pin = “L”.
MS0684-E-02
-5-
2008/12
京公网安备 11010802033920号
EEWORLD
