Advance Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Product Description
The CN8478, CN8474A, CN8472A, and CN8471A are advanced Multichannel
Synchronous Communication Controllers (MUSYCCs) that format and deformat up
to 256 (CN8478), 128 (CN8474A), 64 (CN8472A), or 32 (CN8471A) HDLC
channels in a single CMOS integrated circuit. MUSYCC operates at Layer 2 of the
Open Systems Interconnection (OSI) protocol reference model. MUSYCC provides
a comprehensive, high-density solution for processing HDLC channels for
internetworking applications such as Frame Relay, ISDN D-channel signaling,
X.25, Signaling System 7 (SS7), DXI, ISUP, and LAN/WAN data transport. Under
minimal host supervision, MUSYCC manages a linked list of channel data buffers
in host memory by performing Direct Memory Access (DMA) of the HDLC
channels.
MUSYCC interfaces with eight independent serial data streams, such as T1/E1
signals, and then transfers data across the popular 32-bit Peripheral Component
Interface (PCI) bus to system memory at a rate of up to 66 MHz. Each serial
interface can be operated at up to 8.192 MHz. Logical channels can be mapped as
any combination of DS0 time slots to support ISDN hyperchannels (Nx64 kbps) or
as any number of bits in a DS0 for subchanneling applications (Nx8 kbps).
MUSYCC also includes a 32-bit expansion port for bridging the PCI bus to local
microprocessors or peripherals. A JTAG port enables boundary-scan testing to
replace bed-of-nails board testing.
Device drivers for Linux, VxWorks
®
, and pSOS™ operating systems are
available under a no-fee license agreement from Conexant. The device drivers
include C source code and supporting software documents.
Distinguishing Features
•
•
•
256-, 128-, 64-, or 32-channel HDLC
controller
OSI Layer 2 protocol support
General purpose HDLC (ISO 3309)
– X.25 (LAPB)
– Frame relay (LAPF/ANSI T1.618)
– ISDN D-channel (LAPD/Q.921)
– SS7 support
8, 4, 2, or 1 independent serial interfaces
which support
– T1/E1 data streams
– DC to 8.192 Mbps TDM busses
Configurable logical channels
– Standard DS0 (56, 64 kbps)
– Hyperchannel (Nx64)
– Subchannel (Nx8)
Per-channel protocol mode selection
– 16-bit FCS mode
– 32-bit FCS mode
– SS7 mode (16-bit FCS)
– Transparent mode (unformatted data)
Per-channel DMA buffer management
– Linked list data structures
– Variable size transmit/receive FIFO
Per-channel message length check
– Select no length checking
– Select from two 12-bit registers to
compare message length
– Maximum length 16,384 Bytes
Direct PCI bus interface
– 32-bit, 66 or 33 MHz operation
– Bus master and slave operation
– PCI Version 2.1
Local Expansion Bus interface (EBUS)
– 32-bit multiplexed address/data bus
– Burst access up to 64 Bytes
Low power, 3.3/2.5 V CMOS operation
JTAG boundary scan access port
208-pin PQFP/surface-mount package
BGA
ISDN basic-rate or primary-rate interfaces
ISDN D-channel controller
Routers
Cellular base station switch controller
CSU/DSU
Protocol converter
Packet data switch
Frame relay switches/Frame Relay Access
Devices (FRAD)
DXI network interface
Distributed packet-based communications
system
Access multiplexer/concentrator
•
•
•
•
•
Functional Block Diagram
•
Host
Interface
Channel Group 0 – Serial Interface
DMA
Controller
Tx/Rx-DMAC
Interrupt
Controller
Bit-Level
Processor
Tx/Rx-BLP
Port
Interface
Tx/Rx
Device
Configuration
Registers
•
Channel Group 1 – Serial Interface
Serial Data Bus
Local Bus
Channel Group 2 – Serial Interface
Channel Group 3 – Serial Interface
Channel Group 4 – Serial Interface
Channel Group 5 – Serial Interface
Channel Group 6 – Serial Interface
Channel Group 7 – Serial Interface
Note: Number of serial interfaces is device-dependent.
PCI Bus
PCI
Interface
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Applications
PCI
Configuration
Space
(Function 0)
PCI
Configuration
Space
(Function 1)
Boundary Scan and Test Access
Expanion Bus Interface
100660E
Conexant
Ordering Information
Model Number
CN8471AEPF
CN8472AEPF
CN8474AEPF
CN8478EPF
CN8471AEBG
CN8472AEBG
CN8474AEBG
CN8478EBG
Version
32-Channel
64-Channel
128-Channel
256-Channel
32-Channel
64-Channel
128-Channel
256-Channel
Package
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Ball Grid Array
208-Pin Plastic Ball Grid Array
208-Pin Plastic Ball Grid Array
208-Pin Plastic Ball Grid Array
Temperature Range
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
© 2000,
Conexant Systems, Inc.
All Rights Reserved.
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provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no
responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at
any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to its specifications and product descriptions.
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or field applications
engineer.
100660E
Conexant
Table of Contents
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1.0
System Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
2.0
Host Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
PCI Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
PCI Initialization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PCI Bus Operations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PCI Configuration Space
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Function 0 Network Controller—PCI Master and Slave.
. . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Function 1 Expansion Bus Bridge, PCI Slave
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
PCI Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Host Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
PCI Bus Parity
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
PCI Throughput and Latency Considerations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.2.6.1
PCI Bus Latency
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.2.6.2
Latency Computation—Single Dword Access
. . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.2.6.3
Latency Computation—Burst Access
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
PCI Configuration Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
3.0
Expansion Bus (EBUS)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.10
3.1.11
Initialization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Address and Data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Clock
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Interrupt
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Address Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Data Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Bus Access Interval
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PCI to EBUS Interaction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Microprocessor Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Arbitration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Connection
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
100660E
Conexant
iii
Table of Contents
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
4.0
Serial Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1
4.2
4.3
4.4
4.5
Serial Port Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Bit Level Processor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
DMA Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Interrupt Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Channelized Port Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.6
4.7
Hyperchannels (Nx64)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subchannels (Nx8)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Synchronization Flywheel
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Change-of-Frame Alignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Out-of-Frame
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
4-3
4-4
4-8
4-8
Serial Port Mapping
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Tx and Rx FIFO Buffer Allocation and Management
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.7.1
4.7.2
4.7.3
Example Channel BUFFLOC and BUFFLEN Specification
. . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Receiving Bit Stream
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Transmitting Bit Stream
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.7.3.1
Transmit Data Bit Output Value Determination
. . . . . . . . . . . . . . . . . . . . . . . 4-16
5.0
Memory Organization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1
Memory Architecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1
5.1.2
5.2
5.2.1
Register Map Access and Shared Memory Access
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Memory Access Illustration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Host Interface Level Descriptors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.2.1.1
Global Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.2.1.2
Dual Address Cycle Base Pointer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Channel Group Level Descriptors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.2.2.1
Group Base Pointer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.2.2.2
Service Request
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.2.2.3
Group Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.2.2.4
Memory Protection Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.2.2.5
Port Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.2.2.6
Message Length Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.2.2.7
Time Slot Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.2.2.8
Subchannel Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Channel Level Descriptors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.2.3.1
Channel Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Message Level Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.2.4.1
Using Message Descriptors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.2.4.2
Note for Interrupt Driven Drivers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.2.4.3
Head Pointer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.2.4.4
Message Pointer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.2.4.5
Message Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.2.4.6
Buffer Descriptor.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
Descriptors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.2.2
5.2.3
5.2.4
iv
Conexant
100660E
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Table of Contents
5.2.5
5.2.6
5.2.4.7
Buffer Status Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5.2.4.8
Next Message Pointer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.2.4.9
Data Buffer Pointer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.2.4.10 Message Descriptor Handling
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Interrupt Level Descriptors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
5.2.5.1
Interrupt Queue Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
5.2.5.2
Interrupt Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5.2.5.3
Interrupt Status Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
Interrupt Handling
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.2.6.1
Initialization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.2.6.2
Interrupt Descriptor Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.2.6.3
INTA* Signal Line
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.2.6.4
INTB* Signal Line
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
6.0
Basic Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1
Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1
6.1.2
6.1.3
6.1.4
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
Hard PCI Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Chip Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Group Reset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Example
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-2
6-3
6-3
Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
PCI Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Global Configuration.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Interrupt Queue Configuration.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Channel Group(s) Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Service Request Mechanism
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
MUSYCC Internal Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.6.1
Memory Operations—Inactive Channels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.6.2
Memory Operations—Active Channels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Group Structure
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Group Base Pointer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Global Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Interrupt Queue Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Group Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Memory Protection Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Port Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Message Length Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Transmit Time Slot Map—Channel 0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Transmit Subchannel Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Transmit Channel Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Receive Time Slot Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Receive Subchannel Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Receive Channel Configuration Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Message Lists
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.3
Channel Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
100660E
Conexant
Preliminary Information
v
DIY/Open Source Hardware
京公网安备 11010802033920号
EEWORLD
