VSP 94x2A
Powerful Scan-Rate Converter
including Multistandard Color Decoder
Release Note: Revision bars indicate significant
changes to the previous edition.
1. Introduction
The VSP 94x2A (PRIMUS) is a new component of the
Micronas MEGAVISION
®
IC set in a CMOS embed-
ded DRAM technology. The VSP 94x2A comprises all
main functions of a digital featurebox in one monolithic
IC. The number of features is limited in favor of a low-
cost solution, but no trade-off has been made concern-
ing picture quality.
Table 1–1:
PRIMUS’ versions
Version
9402A (B13)
9412A (B14)
1)
DATA SHEET
The family is ideally suited to work in conjunction with
the deflection processors SDA 9380 (9402/32) and
DDP 3315C (9412/42). In combination with the ’digital
TV decoder’ MDE 9500, double-scan iDTV is possible.
The package is upward pin-compatible to other
medium-range and high-end devices of the VSP 94xy
family. A 50/60 Hz derivative is also available (9432,
9442). The device comprises a digital multistandard
color decoder, an RGB interface with fast-blank capa-
bility (SCART), digital ITU656 input, scaling units
including panorama, embedded DRAM for upconver-
sion, picture improvements, temporal noise reduction,
as well as A/D and D/A converters.
Scan Rate
Conversion
100i/120i
100i/120i
Digital Input
(✓)
1)
✓
Digital Output
(✓)
1)
✓
Analog Output
✓
Input and output cannot be used at same time (pin sharing)
Table 1–2:
Hardware Compatibility and Suited Backend ICs
Hardware Compatible
1)
DDP 3315C
VSP 9402A,
VSP 9405B, VSP 9435B
VSP 9407B, VSP 9437B
VSP 9412A,
VSP 9415B, VSP 9445B
VSP 9417B, VSP 9447B
VSP 9425B, VSP 9427B
1)
Suited Backend IC
SDA 9380
✓
✓
(No ITU656 input possible)
✓
✓
✓
With some restrictions. Please refer to pin description and/or respective application note
4
Aug. 16, 2004; 6251-552-1DS
Micronas
DATA SHEET
VSP 94x2A
– Scan-rate-conversion
• Simple interlaced modes (100/120 Hz): AABB,
AAAA, BBBB (9402A/9412A only)
• No scan-rate-conversion modes (50/60 Hz): AB,
AA, BB (9432A/9442A only)
– Flexible output sync controller
• Flexible positioning of the output signal
• Flexible programming of the output sync raster
• ‘Blank signal’ generation
– Signal manipulations
• Still field
• Insertion of colored background
• Windowing
• Vertical chrominance shift for improved VCR pic-
ture quality
– Sharpness improvement
• Digital color transition improvement (DCTI)
• Peaking (luminance)
– Three D/A converters
• 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) out-
put
• 72 MHz clock frequency
• Two-fold oversampling for anti-imaging
• Simplification of external analog postfiltering
– 1920 active pixel/per line in default configuration
– I
2
C-bus control (400 kHz)
• Selectable I
2
C address
– 1.8 V
±5%
and 3.3 V
±5%
supply voltages
– PMQFP80-1 package
1.1. Features
– Integrated video matrix switch
• Up to seven CVBS inputs, up to two Y/C inputs,
• Three CVBS outputs (Y/C inputs signals are com-
bined to CVBS output format)
• 9 bit amplitude resolution for CVBS, Y/C A/D con-
verter
• AGC (Automatic Gain Control)
– Multi-standard color decoder
• PAL/NTSC/SECAM including all substandards
• Automatic recognition of chroma standard
• Only one crystal necessary for all standards
– RGB-FBL or YUV-H-V input
• 8 bit amplitude resolution for RGB or YUV
• 8 bit amplitude resolution for FBL or H
– ITU656 support (version dependent, refer to next
chapter)
• ITU656 input/output
• DS656 output (double-scan ‘656-like’ output)
– Letterbox detection
– Noise reduction
• Temporal noise reduction
• Field-based temporal noise reduction for lumi-
nance and chrominance
• Different motion detectors for luminance and
chrominance or identical
• Flexible programming of the temporal noise
reduction parameters
• Automatic measurement of the noise level
– Horizontal scaling of the 1f
H
signal
• Split-screen possible with additional PiP or Text
processor
– Flexible digital horizontal scaling of the 2f
H
signal
• Scaling factors: 3, ..., 0.75 including 16:9 compat-
ibility
• 5 zone panorama generator
– Embedded memory
• On-chip memory controller
• Embedded DRAM core for field memory
• SRAM for PAL/SECAM delay line
– Data format 4:2:2
– Flexible clock and synchronization concept
• Horizontal line-locked or free-running mode
• Vertical locked or free-running mode
Micronas
Aug. 16, 2004; 6251-552-1DS
5
Microcontroller MCU
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