V62C1161024L(L)
Ultra Low Power
64K x 16 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 30mA I
CC
at 70ns
- Stand-by: 5
µ
A
(CMOS input/output)
1
µA
(
CMOS input/output, L version)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to 2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOP (II) Package
Functional Description
The V62C1161024L is a Low Power CMOS Static RAM
organized as 65,536 words by 16 bits. Easy memory exp-
ansion is provided by an active LOW (CE) and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
TSOP(II)
Row Select
Vcc
Vss
Memory Array
1024 X 1024
I/O1 - I/O8
I/O9 - I/O16
Data
Cont
Data
Cont
I/O Circuit
Column Select
A10 A11 A12 A13 A14 A15
WE
OE
BHE
BLE
CE
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
1
REV. 1.1
April
2001 V62C1161024L(L)
V62C1161024L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
PT
Tstg
Tbias
Minimum
-0.5
−
-55
-40
Maximum
+4.0
1.0
+150
+85
Unit
V
W
0
C
0
C
* Note:
Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability.
Truth Table
CE
OE
WE
BLE BHE I/O1-I/O8 I/O9-I/O16
Power
Mode
H
L
L
L
L
L
L
L
L
X
L
L
L
X
X
X
H
X
X
H
H
H
L
L
L
H
X
X
L
H
L
L
L
H
X
H
X
H
L
L
L
H
L
X
H
High-Z
Data Out
High-Z
Data Out
Data In
Data In
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
Data Out
Data In
High-Z
Data In
High-Z
High-Z
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Output Disable
Output Disable
* Key:
X = Don’t Care, L = Low, H = High
Recommended Operating Conditions
(T
A
= 0
o
C to +70
o
C / -40
o
C to 85
o
C**)
Parameter
Supply Voltage
Symbol
V
CC
Gnd
V
IH
V
IL
Min
1.8
0.0
1.6
-0.5*
Typ
2.0
0.0
-
-
Max
2.2
0.0
V
CC
+ 0.2
0.4
Unit
V
V
V
V
Input Voltage
*
V
IL
min = -2.0V for pulse width less than t
RC
/2.
**
For Industrial Temperature
2
REV. 1.1
April
2001 V62C1161024L(L)
V62C1161024L(L)
DC Operating Characteristics
(V
cc
= 2V+10%, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to 85
0
C)
Parameter
Input Leakage Current
Output Leakage
Current
Operating Power
Supply Current
Average Operating
Current
Sym
Test Conditions
V
cc
= Max,
V
in
= Gnd to V
cc
CE = V
IH
or V
cc
= Max,
V
OUT
= Gnd to V
cc
CE = V
IL
, V
IN
= V
IH
or V
IL
,
I
OUT
= 0
I
OUT
= 0mA,
Min Cycle, 100% Duty
CE < 0.2V
I
OUT
= 0mA,
Cycle Time=1µs, Duty=100%
-70
-
-
-
-
-
1
1
3
30
3
-
-
-
-
-
-85
1
1
3
25
3
-
-
-
-
-
-100
1
1
3
20
3
-
-
-
-
-
-120
1
1
3
20
3
Min Max Min Max Min Max Min Max
Unit
µA
µA
mA
I
I
LI
I
I
LO
I
CC
I
CC1
I
CC2
mA
mA
Standby Power Supply
Current (TTL Level)
Standby Power Supply
Current (CMOS Level)
Output Low Voltage
Output High Voltage
I
SB
I
SB1
CE = V
IH
CE > V
cc
- 0.2V
V
IN
< 0.2V or
V
IN
> V
cc
- 0.2V
I
OL
= 2 mA
I
OH
= -1 mA
-
0.5
5
1
0.4
-
-
-
-
-
1.6
0.5
5
1
0.4
-
-
-
-
-
1.6
0.5
5
1
0.4
-
-
-
-
-
1.6
0.5
5
1
0.4
-
mA
L
LL
-
-
-
1.6
µA
µA
V
V
V
OL
V
OH
Capacitance
(f = 1MHz, T
A
= 25
0
C)
Parameter*
Input Capacitance
I/O Capacitance
Symbol
C
in
C
I/O
Test Condition
V
in
= 0V
V
in
= V
out
= 0V
Max
7
8
Unit
pF
pF
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
Output Load Condition
70ns/85ns
Load for 100ns/120ns
0.4V to 1.6V
5ns
1.0V
C
L
*
TTL
C
L
= 30pf + 1TTL Load
C
L
= 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
3
REV. 1.1
April
2001 V62C1161024L(L)
V62C1161024L(L)
Read Cycle
(9)
(V
cc
= 2V+0.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
BLE, BHE Enable to Output in Low-Z
BLE, BHE Disable to Output in High-Z
BLE, BHE Access Time
Sym
t
RC
t
AA
t
ACE
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
BLZ
t
BHZ
t
BA
70
-
-
-
10
10
-
5
-
5
-
-
-70
-
70
70
40
-
-
30
-
25
-
25
40
85
-
-
-
10
10
-
5
-
5
-
-
-85
-
85
85
40
-
-
35
-
30
-
30
40
-100
100
-
-
-
10
10
-
5
-
5
-
-
-
100
100
50
-
-
40
-
35
-
35
50
-120
120
-
-
-
10
10
-
5
-
5
-
-
-
120
120
60
-
-
40
-
40
-
40
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Min Max Min Max Min Max Min Max
4,5
3,4,5
4,5
3,4,5
Write Cycle
(11)
(V
cc
=2V+0.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
BLE, BHE Setup to Write End
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WHZ
t
OW
t
BW
70
60
60
0
50
0
30
0
-
5
60
-70
-
-
-
-
-
-
-
-
30
-
-
4
-85
85
70
70
0
60
0
35
0
-
5
70
-
-
-
-
-
-
-
-
35
-
-
-100
100
-120
-
-
-
-
-
-
-
-
120
90
40
0
80
0
45
0
-
5
90
-
-
-
-
-
-
-
-
40
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Min Max Min Max Min Max Min Max
80
80
0
70
0
40
0
-
5
80
40
-
-
REV. 1.1
April
2001 V62C1161024L(L)
V62C1161024L(L)
Timing Waveform of Read Cycle 1
(Address Controlled)
t
RC
Address
t
OH
Data Out
t
AA
Data Valid
Previous Data Valid
Timing Waveform of Read Cycle 2
t
RC
Address
t
AA
CE
t
ACE
t
LZ(4,5)
t
BA
t
BLZ(4,5)
t
OE
High-Z
t
OLZ
t
HZ(3,4,5)
t
BHZ(3,4,5)
(BLE/BHE)
t
OHZ
t
OH
Data Valid
OE
Data Out
Notes
(Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition
t
HZ
(max.) is less than
t
LZ
(min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = V
IL
.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see
AC Test Condition,
Figure A.
5
REV. 1.1
April
2001 V62C1161024L(L)
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