Ultra Low Power/High Speed CMOS SRAM
2M X 8 bit
Green package materials are compliant to RoHS
BH62UV1601
n
FEATURES
Ÿ
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Ÿ
Ultra low power consumption :
V
CC
= 3.6V
Operation current : 12mA (Max.)at 55ns
2mA (Max.) at 1MHz
Standby current : 5.0uA (Typ.) at 3.0V/25
O
C
V
CC
= 1.2V
Data retention current : 2.5uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-55
55ns (Max.) at V
CC
=1.65~3.6V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE1, CE2 and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation, no clock, no refresh
Ÿ
Data retention supply voltage as low as 1.0V
n
DESCRIPTION
The BH62UV1601 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 2,048K by 8 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.6V/25
O
C and maximum access time of 55ns at
1.65V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV1601 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH62UV1601 is made with two chips of 8Mbit SRAM by stacked
multi-chip-package.
The BH62UV1601 is available in 48-ball BGA package.
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=1.8V
10MHz
f
Max.
V
CC
=3.6V
V
CC
=1.8V
1MHz
V
CC
=3.6V
10MHz
f
Max.
1MHz
BH62UV1601AI
Industrial
-40
O
C to +85
O
C
30uA
25uA
2mA
6mA
12mA
1.5mA
5mA
8mA
BGA-48-0608
n
PIN CONFIGURATIONS
n
BLOCK DIAGRAM
1
A
B
C
D
E
F
G
H
NC
NC
DQ0
VSS
VCC
DQ3
NC
A18
2
OE
NC
NC
DQ1
DQ2
NC
A20
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
NC
DQ5
DQ6
NC
WE
A11
6
CE2
NC
DQ4
VCC
VSS
DQ7
NC
A19
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 16384
16384
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
2048
Column Decoder
11
Control
Address Input Buffer
8
Column I/O
Write Driver
Sense Amp
8
Data
Output
Buffer
CE1
CE2
WE
OE
V
CC
GND
A20 A19 A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH62UV1601
1
Revision 1.1
May
2006
BH62UV1601
n
PIN DESCRIPTIONS
Name
A0-A20 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
Function
These 21 address inputs select one of the 2,048K x 8 bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
8 bi-directional ports are used to read data from or write data into the RAM.
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
V
CC
V
SS
Power Supply
Ground
n
TRUTH TABLE
MODE
Chip De-selected
(Power Down)
Output Disabled
Read
Write
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
I/O OPERATION
High Z
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
X
H
L
X
High Z
D
OUT
D
IN
NOTES: H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
n
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
n
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 4.6V
-40 to +125
-60 to +150
1.0
20
RANG
Industrial
AMBIENT
TEMPERATURE
-40
O
C to + 85
O
C
V
CC
1.65V ~ 3.6V
C
C
O
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
O
W
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
10
15
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns
R0201-BH62UV1601
1. This parameter is guaranteed and not 100% tested.
2
Revision 1.1
May
2006
BH62UV1601
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
I
CC1
I
CCSB
I
CCSB1
PARAMETER
Power Supply
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current
–
TTL
Standby Current
–
CMOS
V
IN
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
V
I/O
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
or OE = V
IH
V
CC
= Max, I
OL
= 0.1mA
V
CC
= Max, I
OL
= 2.0mA
V
CC
= Min, I
OH
= -0.1mA
V
CC
= Min, I
OH
= -1.0mA
CE1 = V
IL
, CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX(4)
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
O
O
TEST CONDITIONS
MIN.
1.65
-0.3
(2)
1.4
2.2
--
--
--
V
CC
-0.2
2.4
--
--
--
--
TYP.
(1)
--
--
--
--
--
--
--
6
8
1.0
1.5
--
5.0
5.0
(5)
MAX.
3.6
0.4
0.8
V
CC
+0.3
(3)
1
1
0.2
0.4
--
8
12
1.5
2.0
0.5
1.0
25
30
UNITS
V
V
V
uA
uA
V
V
mA
mA
mA
uA
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. V
CC
=3.0V
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +85 C)
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
O
TEST CONDITIONS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=1.2V
MIN.
1.0
--
0
TYP.
(1)
--
2.5
--
--
MAX.
--
15
--
--
UNITS
V
uA
ns
ns
See Retention Waveform
t
RC (2)
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
DR
≧1.0V
V
CC
V
IH
V
CC
V
CC
t
CDR
CE1≧V
CC
- 0.2V
t
R
V
IH
CE1
R0201-BH62UV1601
3
Revision 1.1
May
2006
BH62UV1601
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
DR
≧1.0V
V
CC
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
OHZ
, t
WHZ
, t
OW
Output Load
Others
V
CC
/ 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
ALL INPUT PULSES
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
CYCLE TIME : 55ns
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
MIN.
55
--
--
--
--
10
10
5
--
--
--
10
TYP.
--
--
--
--
--
--
--
--
--
--
--
--
MAX.
--
55
55
55
30
--
--
--
25
25
25
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
O
O
t
AVAX
t
AVQX
t
E1LQV
t
E2LQV
t
GLQV
t
E1LQX
t
E2LQX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
R0201-BH62UV1601
4
Revision 1.1
May
2006
BH62UV1601
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
(1,3,4)
t
AA
t
OH
READ CYCLE 2
CE1
t
ACS1
CE2
t
CLZ
D
OUT
(5)
t
ACS2
t
CHZ1
, t
CHZ2
(5)
READ CYCLE 3
(1, 4)
t
RC
ADDRESS
t
AA
OE
t
OE
CE1
t
CLZ1
CE2
t
CLZ2
D
OUT
(5)
t
OH
t
OLZ
t
ACS1
t
OHZ
t
CHZ1
(5)
(1,5)
t
ACS2
(5)
t
CHZ2
(2,5)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH
.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BH62UV1601
5
Revision 1.1
May
2006
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