RDC
®
RISC DSP Communication
R1120I
16-BIT RISC MICROCONTROLLER
16-BIT RISC MICROCONTROLLER
R1120I
Brief Sheet
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page 1 of 5
REV 1.0 Dec.07 2005
RDC
®
RISC DSP Communication
R1120I
16-BIT RISC MICROCONTROLLER
1.
Features
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PSRAM (Pseudo static RAM) interface with
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Five-stage pipeline
RISC architecture
Integrated PLL (*1~*8)
Maximum frequency: 40 MHz; the external bus,
internal bus and core are operating in the same
clock base
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Static & synthesizable design
Bus interface
- A multiplexed address and data bus which is
compatible with the 80C186 microprocessor
- Supports a direct address bus A[19:0]
- 1M-byte memory address space
- 64K-byte I/O space
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Software is compatible with the 80C186
microprocessor
Supports two asynchronous serial channels with
hardware handshaking signals
Supports CPU ID
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Supports 32 PIO pins
auto-refresh control
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Three independent 16-bit timers and one
independent watchdog timer
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The Interrupt controller with seven maskable
external interrupts and one non-maskable external
interrupt
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Two independent DMA channels
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Programmable chip-select logic for memory or I/O
bus cycle decoder
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Programmable wait-state generators
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The I/O pin output is 3.3 volt level and the input
3.3 to 5 volt tolerance.
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3.3V operation voltage
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Supports serial port/ DMA transfers
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With 8-bit or 16-bit boot ROM bus size
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A green product
Package Type
- PQFP100 pins & LQFP100 pins
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page
2 of
5
REV
1.0
Dec. 07
2005
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