EPH1100PDC-42.000M-G2
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Sep 15, 2020)
191 SVHC
ITEM DESCRIPTION
Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 8 Pin DIP Metal Thru-Hole 42.000MHz ±100ppm
-20°C to +70°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Pin 1 Input Voltage (Vih and Vil)
Standby Current
Peak to Peak Jitter (tPK)
RMS Period Jitter (tRMS)
Start Up Time
Storage Temperature Range
42.000MHz
±100ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating
Temperature Range,Supply Voltage Change, Output Load Change, First Year Aging at 25°C, Shock, and Vibration)
±5ppm/year Maximum
-20°C to +70°C
5.0Vdc ±10%
45mA Maximum (Unloaded)
Vdd-0.4Vdc Minimum (IOH = -16mA)
0.4Vdc Maximum (IOL = +16mA)
4nSec Maximum (Measured at 20% to 80% of waveform)
50 ±10(%) (Measured at 1.4Vdc with TTL Load; Measured at 50% of waveform with HCMOS Load)
50pF HCMOS Load Maximum
CMOS
Power Down (Disabled Output: Logic Low)
+2.0Vdc Minimum to enable output, +0.8Vdc Maximum to disable output, No Connect to enable output.
50µA Maximum (Pin 1 = Ground)
100pSec Maximum, 50pSec Typical
13pSec Maximum, 8pSec Typical
10mSec Maximum
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
Gross Leak Test
Lead Integrity
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014, Condition A
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2004
MIL-STD-202, Method 213, Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 03/25/2014 | Page 1 of 8
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EPH1100PDC-42.000M-G2
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State or
Power Down
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass
capacitor close (less than 2mm) to the package ground and supply voltage pin is required.
Note 2: A low input capacitance (<12pF), 10X Attentuation Factor, High Impedance (>10Mohms), and
High bandwidth (>300MHz) passive probe is recommended.
Note 3: Capacitance value CL includes sum of all probe and fixture capacitance. See applicable specification sheet
for ‘Load Drive Capability’.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 03/25/2014 | Page 4 of 8
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
PART NUMBER DATA SHEET
EPH1100PDC-42.000M-G2
Gull Wing Option G Dimensions &
Recommended Solder Pad Layout
1.80 ±0.15
7.62 ±0.20
5.60
13.08 7.62 ±0.20
±0.40
1.02
(X4)
3.81 (X4)
6.60
Tape & Reel Dimensions
4.0 ±0.2
2.0 ±0.1
DIA 1.5 +0.1/-0.0
0.60 MAX
0.10 MAX
11.0
±0.1
B0
24.0
±0.3
24.0
±0.2
A0
13.78
±0.10
K0
2.28 ±0.10
Direction of Unreeling
Quantity Per Reel: 700 Units Maximum
All Dimensions in Millimeters
Compliant to EIA-481
1.5 MIN
DIA 40 MIN
Access Hole at
Slot Location
22.4 MAX
360 MAX
DIA 50 MIN
DIA 20.2 MIN
2.5 MIN Width
10.0 MIN Depth
Tape slot in Core
for Tape Start
24.4 +2.0/-0.0
DIA 13.0 ±0.2
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 03/25/2014 | Page 5 of 8
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
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