EPM5192GC84-2 datasheet, PDF - EEWORLD Datasheet

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EPM5192GC84-2: DescriptionUV PLD, 45ns, CMOS, CPGA84, WINDOWED, CERAMIC, PGA-84; CategoryProgrammable logic devices Programmable logic; File Size650KB，34 Pages; ManufacturerAltera (Intel)

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EPM5192GC84-2 Overview

UV PLD, 45ns, CMOS, CPGA84, WINDOWED, CERAMIC, PGA-84

EPM5192GC84-2 Parametric

Parameter Name	Attribute value
Maker	Altera (Intel)
Parts packaging code	PGA
package instruction	WPGA,
Contacts	84
Reach Compliance Code	unknown
Other features	192 MACROCELLS; SHARED INPUT/CLOCK; SHARED PRODUCT TERMS
maximum clock frequency	40 MHz
JESD-30 code	S-CPGA-P84
length	28.448 mm
Dedicated input times	7
Number of I/O lines	64
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	7 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	WPGA
Package shape	SQUARE
Package form	GRID ARRAY, WINDOW
Programmable logic type	UV PLD
propagation delay	45 ns
Certification status	Not Qualified
Maximum seat height	4.96 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	28.448 mm
Base Number Matches	1

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MAX 5000

Programmable Logic

Device Family

Data Sheet

May 1999, ver. 5

Features...

Advanced Multiple Array MatriX (MAX

) 5000 architecture

combining speed and ease-of-use of PAL devices with the density of

programmable gate arrays

Complete family of high-performance, erasable CMOS EPROM

erasable programmable logic devices (EPLDs) for designs ranging

from fast 28-pin address decoders to 100-pin LSI custom peripherals

600 to 3,750 usable gates (see Table 1)

Fast, 15-ns combinatorial delays and 76.9-MHz counter frequencies

Configurable expander product-term distribution allowing more

than 32 product terms in a single macrocell

28 to 100 pins available in dual in-line package (DIP), J-lead chip

carrier, pin-grid array (PGA), and quad flat pack (QFP) packages

Programmable registers providing D, T, JK, and SR flipflop

functionality with individual clear, preset, and clock controls

Programmable security bit for protection of proprietary designs

Software design support featuring the Altera

MAX+PLUS

development system on Windows-based PCs, as well as

Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC

System/6000 workstations

Table 1. MAX 5000 Device Features

Feature

Usable gates

Macrocells

Logic array blocks (LABs)

Expanders

Routing

Maximum user I/O pins

(ns)

ASU

(ns)

CNT

(MHz)

EPM5032

600

Global

76.9

EPM5064

1,250

128

PIA

EPM5128

2,500

128

256

PIA

EPM5130

2,500

128

256

PIA

EPM5192

3,750

192

384

PIA

MAX 5000

Altera Corporation

A-DS-M5000-05

709

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