Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[1]
0
°
C to +70
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C167A-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB
Description
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
[2]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
[4]
GND < V
I
< V
CC
GND < V
O
< V
CC
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC =
Max., I
OUT
= 0 mA
Max. V
CC
, CE > V
IH
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min.,
I
OL
= 12.0 mA, 8.0 mA Mil
2.2
−0.5
−10
−10
Min.
2.4
0.4
V
CC
0.8
+10
+10
−350
90
40
7C167A-35
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB
Description
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
[2]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
[4]
GND < V
I
< V
CC
GND < V
O
< V
CC
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC =
Max., I
OUT
= 0 mA
Max. V
CC
, CE > V
IH
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min.,
I
OL
= 12.0 mA, 8.0 mA Mil
2.2
−0.5
−10
−10
Min.
2.4
0.4
V
CC
0.8
+10
+10
−350
90
20
2.2
−0.5
−10
−10
Max.
2.2
−0.5
−10
−10
Max.
7C167A-20
Min.
2.4
0.4
V
CC
0.8
+10
+10
−350
90
40
7C167A-45
Min.
2.4
0.4
V
CC
0.8
+10
+10
−350
90
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
2.2
−0.5
−10
−10
Max.
7C167A-25
Min.
2.4
0.4
V
CC
0.8
+10
+10
−350
90
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Notes:
1. T
A
is the case temperature.
2. V
IL
min. =
−
3.0V for pulse durations less than 30 ns.
3. Duration of the short circuit should not exceed 30 seconds.
4. A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
Document #: 38-05027 Rev. **
Page 2 of 9
CY7C167A
Capacitance
[5]
Parameter
C
IN
C
OUT
C
CE
Description
Input Capacitance
Output Capacitance
Chip Enable Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
6
Unit
pF
pF
pF
AC Test Loads and Waveforms
R1 329
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
202
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
202
Ω
R1 329
Ω
ALL INPUT PULSES
3.0V
GND
10%
90%
90%
10%
< 5 ns
C167A-4
< 5 ns
(a)
(b)
C167A-3
THÉVENIN EQUIVALENT
125
Ω
OUTPUT
1.9V
Switching Characteristics
Over the Operating Range
[6]
7C167A-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[7]
7C167A-20
Min.
20
Max.
7C167A-25
Min.
25
Max.
7C167A-35
Min.
30
Max.
7C167A-45
Min.
Max.
Unit
ns
Description
Min.
15
Max.
15
5
15
5
8
0
15
15
12
12
0
0
12
10
0
7
5
5
20
15
15
0
0
15
10
0
0
5
5
20
5
20
5
8
0
20
20
20
20
0
0
15
10
0
7
5
25
5
25
5
10
0
20
25
25
25
0
0
20
15
0
7
5
30
5
35
5
15
0
20
40
30
30
0
0
20
15
0
10
5
15
25
15
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE HIGH to High Z
[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
[9]
WRITE CYCLE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[7, 8]
WE HIGH to Low Z
[7]
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. At any given temperature and voltage condition, t
HZ
is less than t
LZ
for any given device.
8. t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05027 Rev. **
Page 3 of 9
CY7C167A
Switching Waveforms
Read Cycle No. 1
[10, 11]
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C167A-5
t
RC
Read Cycle No. 2
[10, 12]
t
RC
CE
t
ACE
t
LZCE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
PU
50%
DATA VALID
t
PD
I
CC
50%
I
SB
C167A-6
t
HZCE
HIGH
IMPEDANCE
Write Cycle No. 1 (WE Controlled)
[9]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
DATA UNDEFINED
C167A-7
t
AW
t
PWE
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
Notes:
10. WE is high for read cycle.
11. Device is continuously selected, CE = V
IL
.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05027 Rev. **
Page 4 of 9
CY7C167A
Switching Waveforms
(continued)
Write Cycle No. 2 (CE Controlled)
[9, 13]
t
WC
ADDRESS
t
SA
CE
t
AW
t
PWE
WE
t
SD
DATA IN
t
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C167A-8
t
SCE
t
HA
t
HD
DATA
IN
VALID
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
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