TMS470R1B512
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
FEATURES
•
•
High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
– 24-MHz System Clock (60-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Utilizes Big-Endian Format
Integrated Memory
– 512K-Byte Program Flash
•
2 Banks With 14 Contiguous Sectors
•
Internal State Machine for Programming
and Erase
– 32K-Byte Static RAM (SRAM)
27 Dedicated General-Purpose Input/Output
(GIO) Pins, 1 Input-Only GIO Pin, and 59
Additional Peripheral I/Os
Operating Features
– Core Supply Voltage (V
CC
): 1.81 V – 2.05 V
– I/O Supply Voltage (V
CCIO
): 3.0 V – 3.6 V
– Low-Power Modes: STANDBY and HALT
– Extended Industrial Temperature Range
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
– Interrupt Expansion Module (IEM)
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
•
•
•
•
•
•
•
•
•
•
•
•
(1)
•
•
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
Seven Communication Interfaces:
– Three Serial Peripheral Interfaces (SPIs)
•
255 Programmable Baud Rates
– Two Serial Communications Interfaces
(SCIs)
•
2
24
Selectable Baud Rates
•
Asynchronous/Isosynchronous Modes
•
Two High-End CAN Controllers (HECCs)
•
32-Mailbox Capacity Each
•
Fully Compliant With CAN Protocol,
Version 2.0B
High-End Timer (HET)
– 32 Programmable I/O Channels:
•
24 High-Resolution Pins
•
8 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
•
128-Instruction Capacity
16-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 128-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55
µs
Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
Eight External Interrupts
Flexible Interrupt Handling
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1
(1)
(JTAG) Test-Access Port
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
The test-access port is compatible with the IEEE Standard
1149.1-1990,
IEEE Standard Test-Access Port and Boundary
Scan Architecture
specification. Boundary scan is not
supported on this device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
Copyright © 2005–2006, Texas Instruments Incorporated
ADVANCE INFORMATION
TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
www.ti.com
TMS470R1B512 144-Pin PGE Package (Top View)
ADIN[0]
ADIN[1]
ADIN[2]
ADIN[3]
ADIN[4]
ADIN[15]
ADIN[5]
ADIN[6]
ADIN[7]
ADEVT
SPI3ENA
SPI3SCS
SPI3SIMO
SPI3SOMI
SPI3CLK
V
CC
V
SS
SCI1RX
SCI1TX
SCI1CLK
CAN1HTX
CAN1HRX
V
CC
V
SS
GIOB[7]
CLKOUT
V
CCIO
V
SSIO
HET[9]
HET[8]
GIOB[6]
GIOB[5]
TCK
TDO
TDI
PLLDIS
ADIN[11]
ADIN[14]
ADIN[10]
ADIN[13]
ADIN[9]
ADIN[12]
ADIN[8]
AD
REFHI
AD
REFLO
V
CCAD
V
SSAD
TMS
TMS2
GIOC[0]
HET[23]
HET[25]
HET[26]
HET[27]
V
SS
V
CC
HET[0]
HET[1]
V
SS
V
CC
FLTP2
FLTP1
V
CCP
V
SS
HET[2]
HET[3]
HET[4]
HET[5]
HET[6]
HET[7]
GIOC[1]
GIOC[2]
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
AWD
HET[18]
HET[19]
HET[20]
HET[21]
HET[22]
SPI2SCS
SPI2ENA
SPI2SOMI
SPI2SIMO
SPI2CLK
GIOB[4]
GIOB[3]
GIOB[2]
GIOB[1]
CAN2HRX
CAN2HTX
V
CC
V
SS
V
CCIO
V
SSIO
HET[24]
HET[31]
HET[30]
HET[29]
HET[28]
GIOB[0]
SCI2CLK
SCI2TX
SCI2RX
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOA[1]/INT[1]/ECLK
GIOA[0]/INT[0]
(A)
TEST
TRST
A.
GIOA[0]/INT0 (pin 39) is an input-only GIO pin.
2
SPI1ENA
SPI1SCS
SPI1SIMO
SPI1SOMI
SPI1CLK
GIOC[3]
GIOC[4]
GIOC[5]
GIOC[6]
GIOC[7]
V
SS
OSCOUT
OSCIN
V
CC
RST
V
SSIO
V
CCIO
GIOD[3]
GIOD[2]
GIOD[1]
GIOD[0]
HET[17]
HET[16]
HET[15]
HET[14]
HET[13]
HET[12]
HET[11]
HET[10]
V
SS
V
CC
PORRST
GIOA[7]/INT[7]
GIOA[6]/INT[6]
GIOA[5]/INT[5]
GIOA[4]/INT[4]
ADVANCE INFORMATION
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TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
DESCRIPTION
The TMS470R1B512
(1)
device is a member of the Texas Instruments (TI) TMS470R1x family of
general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The B512 microcontroller
offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU),
resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit
RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The B512 utilizes the
big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The B512 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The B512 device contains the following:
•
ARM7TDMI 16/32-Bit RISC CPU
•
TMS470R1x system module (SYS) with 470+ enhancements [including an interrupt expansion module (IEM)
and a 16-channel direct-memory access (DMA) controller]
•
512K-byte flash
•
32K-byte SRAM
•
Zero-pin phase-locked loop (ZPLL) clock module
•
Analog watchdog (AWD) timer
•
Real-time interrupt ( RTI) module
•
Three serial peripheral interface (SPI) modules
•
Two serial communications interface (SCI) modules
•
Two high-end CAN controller (HECC) modules
•
10-bit multi-buffered analog-to-digital converter (MibADC) with 16 input channels
•
High-end timer (HET) controlling 32 I/Os
•
External clock prescale (ECP) module
•
Up to 86 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include:
•
Address decoding
•
Memory protection
•
Memory and peripherals bus supervision
•
Reset and abort exception management
•
Expanded interrupt capability with prioritization for all internal interrupt sources
•
Device clock control
•
Direct-memory access (DMA) and control
•
Parallel signature analysis (PSA).
This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt
priority, and a device memory map. For a more detailed functional description of the SYS module, see the
TMS470R1x System Module Reference Guide
(literature number SPNU189). For a more detailed functional
description of the IEM module, see the
TMS470R1x Interrupt Expansion Module (IEM) Reference Guide
(literature number SPNU211). For a more detailed functional description of the DMA module, see the
TMS470R1x Direct Memory Access (DMA) Controller Reference Guide
(literature number SPNU194).
The B512 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
(1)
The TMS470R1B512 device name will be referred to as either the full device name or as B512 throughout the remainder of this
document.
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ADVANCE INFORMATION
TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
www.ti.com
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed
information on the F05 devices flash, see the
F05 Flash
section of this data sheet and the
TMS470R1x F05
Flash Reference Guide
(literature number SPNU213).
The B512 device has seven communication interfaces: three SPIs, two SCIs, and two HECCs. The SPI provides
a convenient method of serial interaction for high-speed communications between similar shift-register type
devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the
CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The HECC is ideal for applications operating in
noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed
wiring. For more detailed functional information on the SPI, SCI, and HECC peripherals, see the specific
reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
For more detailed functional information on the HET, see the
TMS470R1x High-End Timer (HET) Reference
Guide
(literature number SPNU199).
The B512 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-
resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For
more detailed information on the HET XOR-share feature, see the
TMS470R1x High-End Timer (HET)
Reference Guide
(literature number SPNU199).
The B512 device has a 10-bit-resolution, 16-channel sample-and-hold MibADC. The MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B512 device modules. For more
detailed functional information on the ZPLL, see the
TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide
(literature number SPNU212).
NOTE:
ADVANCE INFORMATION
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The B512 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide
(literature number SPNU202).
4
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TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
Device Characteristics
The B512 device is a derivative of the F05 system emulation device SE470R1VB8AD.
Table 1
identifies all the
characteristics of the B512 device except the SYSTEM and CPU, which are generic.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1B512
MEMORY
For the number of memory selects on this device, see
Table 3,
Memory Selection Assignment.
INTERNAL MEMORY
Pipeline/Non-Pipeline
512K-Byte flash
32K-Byte SRAM
Flash is pipeline-capable.
The B512 RAM is implemented in one 32K array selected by two
memory-select signals (see
Table 3,
Memory Selection Assignment).
PERIPHERALS
For the device-specific interrupt priority configurations, see
Table 7,
Interrupt Priority (IEM and CIM).
And for the 1K peripheral address
ranges and their peripheral selects, see
Table 5,
A512 Peripherals, System Module, and Flash Base Addresses.
CLOCK
GENERAL-PURPOSE I/Os
ECP
SCI
CAN
(HECC and/or SCC)
SPI
(5-pin, 4-pin or 3-pin)
ZPLL
27 I/O
1 Input only
YES
2 (3-pin)
2 HECCs
3 (5-pin)
SCI1 and SCI2
Two high-end CAN controller modules (HECC1 and HECC2)
SPI1, SPI2, and SPI3
The B512 device has both the logic and registers for a full 32-I/O HET
implemented and all 32 pins are available externally.
The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent
of whether or not the odd pin is available externally. If an odd pin is
available externally and shared, then the odd pin can only be used as a
general-purpose I/O. For more information on HR SHARE, see the
TMS470R1x High-End Timer (HET) Reference Guide
(literature number
SPNU199).
The B512 device has both the logic and registers for a full 16-channel
MibADC implemented and all 16 pins are available externally.
Zero-pin PLL has no external loop filter pins.
Ports A, B, and C each have eight (8) external pins.
Port D has four (4) external pins.
COMMENTS
HET with XOR Share
32 I/O
HET RAM
MibADC
CORE VOLTAGE
I/O VOLTAGE
PINS
PACKAGE
128-Instruction Capacity
10-bit, 16-channel 128-word
FIFO
1.81 – 2.05 V
3.0 – 3.6 V
144
PGE
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