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TN2640N3

Description
N-channel enhancement-mode vertical dmos fets
CategoryDiscrete semiconductor    The transistor   
File Size457KB,4 Pages
ManufacturerSupertex
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TN2640N3 Overview

N-channel enhancement-mode vertical dmos fets

TN2640N3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSupertex
Parts packaging codeTO-92
package instructionCYLINDRICAL, O-PBCY-T3
Contacts3
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresLOW THRESHOLD
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage400 V
Maximum drain current (ID)0.22 A
Maximum drain-source on-resistance5 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)25 pF
JEDEC-95 codeTO-92
JESD-30 codeO-PBCY-T3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeROUND
Package formCYLINDRICAL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)1 W
Certification statusNot Qualified
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
TN2640
TN2640
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
400V
R
DS(ON)
(max)
5.0Ω
V
GS(th)
(max)
2.0V
I
D(ON)
(min)
2.0A
Order Number / Package
SO-8
TN2640LG
TO-92
TN2640N3
DPAK
TN2640K4
Die
TN2640ND
MIL visual screening available.
Features
Low threshold — 2.0V max.
High input impedance
Low input capacitance
Fast switching speeds
Low on resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex's well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Package Options
D (TAB)
G
S
SGD
TO-92
TO-252
(D-PAK)
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
NC
NC
S
G
1
2
3
4
8
7
6
5
D
D
D
D
top view
SO-8
Note: See Package Outline section for dimensions.
12/19/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1

TN2640N3 Related Products

TN2640N3 TN2640LG
Description N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets
Is it Rohs certified? incompatible incompatible
Maker Supertex Supertex
Parts packaging code TO-92 SOIC
package instruction CYLINDRICAL, O-PBCY-T3 SMALL OUTLINE, R-PDSO-G8
Contacts 3 8
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Other features LOW THRESHOLD LOW THRESHOLD
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 400 V 400 V
Maximum drain current (ID) 0.22 A 0.26 A
Maximum drain-source on-resistance 5 Ω 5 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss) 25 pF 25 pF
JEDEC-95 code TO-92 MS-012AA
JESD-30 code O-PBCY-T3 R-PDSO-G8
JESD-609 code e0 e0
Number of components 1 1
Number of terminals 3 8
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 150 °C 150 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
Package shape ROUND RECTANGULAR
Package form CYLINDRICAL SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Polarity/channel type N-CHANNEL N-CHANNEL
Maximum power dissipation(Abs) 1 W 1 W
Certification status Not Qualified Not Qualified
surface mount NO YES
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE GULL WING
Terminal location BOTTOM DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
transistor applications SWITCHING SWITCHING
Transistor component materials SILICON SILICON
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