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TN0110N3

Description
N-channel enhancement-mode vertical dmos fets
CategoryDiscrete semiconductor    The transistor   
File Size28KB,4 Pages
ManufacturerSupertex
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TN0110N3 Overview

N-channel enhancement-mode vertical dmos fets

TN0110N3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSupertex
Parts packaging codeTO-92
package instructionTO-92, 3 PIN
Contacts3
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresLOW THRESHOLD, LOGIC LEVEL COMPATIBLE
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage100 V
Maximum drain current (Abs) (ID)0.5 A
Maximum drain current (ID)0.35 A
Maximum drain-source on-resistance3 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)8 pF
JEDEC-95 codeTO-92
JESD-30 codeO-PBCY-T3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeROUND
Package formCYLINDRICAL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)1 W
Certification statusNot Qualified
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
TN0106
TN0110
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
60V
100V
R
DS(ON)
(max)
3.0Ω
3.0Ω
I
D(ON)
(min)
2A
2A
V
GS(th)
(max)
2.0V
2.0V
Order Number / Package
TO-92
TN0106N3
TN0110N3
Die
TN0110ND
7
MIL visual screening available
Features
s
Low threshold — 2.0V max.
s
High input impedance
s
Low input capacitance — 50pF typical
s
Fast switching speeds
s
Low on resistance
s
Free from secondary breakdown
s
Low input and output leakage
s
Complementary N- and P-channel devices
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex’s well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Applications
s
Logic level interfaces – ideal for TTL and CMOS
s
Solid state relays
s
Battery operated systems
s
Photo voltaic drives
s
Analog switches
s
General purpose line drivers
s
Telecom switches
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
Note: See Package Outline section for dimensions.
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
SGD
TO-92
7-35

TN0110N3 Related Products

TN0110N3 TN0106N3
Description N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets
Is it Rohs certified? incompatible incompatible
Maker Supertex Supertex
Parts packaging code TO-92 TO-92
package instruction TO-92, 3 PIN CYLINDRICAL, O-PBCY-T3
Contacts 3 3
Reach Compliance Code unknown compliant
ECCN code EAR99 EAR99
Other features LOW THRESHOLD, LOGIC LEVEL COMPATIBLE LOW THRESHOLD, LOGIC LEVEL COMPATIBLE
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 100 V 60 V
Maximum drain current (Abs) (ID) 0.5 A 0.5 A
Maximum drain current (ID) 0.35 A 0.35 A
Maximum drain-source on-resistance 3 Ω 3 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss) 8 pF 8 pF
JEDEC-95 code TO-92 TO-92
JESD-30 code O-PBCY-T3 O-PBCY-T3
JESD-609 code e0 e0
Number of components 1 1
Number of terminals 3 3
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 150 °C 150 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
Package shape ROUND ROUND
Package form CYLINDRICAL CYLINDRICAL
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Polarity/channel type N-CHANNEL N-CHANNEL
Maximum power dissipation(Abs) 1 W 1 W
Certification status Not Qualified Not Qualified
surface mount NO NO
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE THROUGH-HOLE
Terminal location BOTTOM BOTTOM
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
transistor applications SWITCHING SWITCHING
Transistor component materials SILICON SILICON

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Index Files: 624  53  2666  1009  1322  13  2  54  21  27 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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