HY27LF081G2M-VEP datasheet, PDF

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HY27LF081G2M-VEP: Description1gbit (128mx8bit / 64mx16bit) nand flash memory; File Size475KB，48 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY27LF081G2M-VEP Overview

1gbit (128mx8bit / 64mx16bit) nand flash memory

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Preliminary

HY27UF(08/16)1G2M Series

HY27SF(08/16)1G2M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

Document Title

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory

Revision History

Revision

No.

0.0

1) Initial Draft.

1) Correct Fig.10 Sequential out cycle after read

2) Add the text to Fig.1, Table.1, Table.2

- text : IO15 - IO8 (x16 only)

3) Delete ‘3.2 Page program NOTE 1.

- Note : if possible it is better to remove this constrain

4) Change the text ( page 10,13, 45)

- 2.2 Address Input : 28 Addresses -> 27 Addresses

- 3.7 Reset : Fig.29 -> Fig.30

- 5.1 Automatic page read after power up : Fig.30 -> Fig.29

5) Add 5.3 Addressing for program operation & Fig.34

1) Change TSOP, WSOP, FBGA package dimension & figures.

- Change TSOP, WSOP, FBGA package mechanical data

- Change FBGA thickness (1.2 -> 1.0 mm)

2) Correct TSOP, WSOP Pin configurations.

- 38th NC pin has been changed Lockpre(figure

3,4)

3) Edit figure 15,19 & table 4

4) Add Bad Block Management

5) Change Device Identifier 3rd Byte

- 3rd Byte ID is changed. (reserved -> don't care)

- 3rd Byte ID table is deleted.

1) Add Errata

tCLS

Specification

Relaxed value

tCLH

tWP

tALS

tALH

tDS

tWC

History

Draft Date

Aug. 2004

Remark

Preliminary

0.1

Sep. 2004

Preliminary

0.2

Oct. 2004

Preliminary

0.3

0.4

2) LOCKPRE is changed to PRE.

- Texts, Table, Figures are changed.

3) Add Note.4 (table.14)

4) Block Lock Mechanism is deleted.

- Texts, Table, figures are deleted.

5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)

- Texts & Figures are added.

6) Edit the figures. (#10~25)

1) Change AC characteristics(tREH)

before: 20ns -> after: 30ns

2) Edit Note.1 (page. 21)

3) Edit the Application note 1,2

4) Edit The Address cycle map (x8, x16)

Nov.29 2004

Preliminary

Jan.19 2005

Preliminary

Rev 0.7 / Apr. 2005

Preliminary

HY27UF(08/16)1G2M Series

HY27SF(08/16)1G2M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

1. SUMMARY DESCRIPTION

The HYNIX HY27(U/S)F(08/16)1G2M series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 1.8V

Vcc Power Supply and in 3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old

data is erased.

The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected

Flash cells.

A program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in

typical 2ms on a 128K-byte(X8 device) block.

Data in the page mode can be read out at 60ns

(1)

cycle time per word. The I/O pins serve as the ports for address and

data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-

ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where

required, and internal verification and margining of data.

The modifying can be locked using the WP# input pin.

The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-

tiple memories the RB# pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27(U/S)F(08/16)1G2M extended reliability of 100K pro-

gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the

code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-

tion.

The copy back function allows the optimization of defective blocks management: when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is copied into the

flash array. This pipelined program operation improves the program throughput when long files are written inside the

memory.

A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-

secutive pages have to be streamed out.

This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension.

The HYNIX HY27(U/S)F(08/16)1G2M series is available in 48 - TSOP1 12 x 20 mm , 48 - WSOP1 12 x 17 mm,

FBGA 9.5 x 12 mm.

1.1 Product List

PART NUMBER

HY27SF081G2M

HY27SF161G2M

HY27UF081G2M

HY27UF161G2M

ORIZATION

x16

VCC RANGE

1.70 - 1.95 Volt

63FBGA / 48TSOP1 / 48WSOP1

2.7V - 3.6 Volt

PACKAGE

NOTE:

1. This parameters is applied to the errata.

Rev 0.7 / Apr. 2005

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