Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
1) Initial Draft.
1) Correct Fig.10 Sequential out cycle after read
2) Add the text to Fig.1, Table.1, Table.2
- text : IO15 - IO8 (x16 only)
3) Delete ‘3.2 Page program NOTE 1.
- Note : if possible it is better to remove this constrain
4) Change the text ( page 10,13, 45)
- 2.2 Address Input : 28 Addresses -> 27 Addresses
- 3.7 Reset : Fig.29 -> Fig.30
- 5.1 Automatic page read after power up : Fig.30 -> Fig.29
5) Add 5.3 Addressing for program operation & Fig.34
1) Change TSOP, WSOP, FBGA package dimension & figures.
- Change TSOP, WSOP, FBGA package mechanical data
- Change FBGA thickness (1.2 -> 1.0 mm)
2) Correct TSOP, WSOP Pin configurations.
- 38th NC pin has been changed Lockpre(figure
3,4)
3) Edit figure 15,19 & table 4
4) Add Bad Block Management
5) Change Device Identifier 3rd Byte
- 3rd Byte ID is changed. (reserved -> don't care)
- 3rd Byte ID table is deleted.
1) Add Errata
tCLS
Specification
Relaxed value
0
5
tCLH
10
15
tWP
25
40
tALS
0
5
tALH
10
15
tDS
20
25
tWC
50
60
tR
25
27
History
Draft Date
Aug. 2004
Remark
Preliminary
0.1
Sep. 2004
Preliminary
0.2
Oct. 2004
Preliminary
0.3
0.4
2) LOCKPRE is changed to PRE.
- Texts, Table, Figures are changed.
3) Add Note.4 (table.14)
4) Block Lock Mechanism is deleted.
- Texts, Table, figures are deleted.
5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)
- Texts & Figures are added.
6) Edit the figures. (#10~25)
1) Change AC characteristics(tREH)
before: 20ns -> after: 30ns
2) Edit Note.1 (page. 21)
3) Edit the Application note 1,2
4) Edit The Address cycle map (x8, x16)
Nov.29 2004
Preliminary
Jan.19 2005
Preliminary
Rev 0.7 / Apr. 2005
1
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Revision History
Revision
No.
History
1) Correct AC characteristics(tREH)
before: 30ns-> after: 20ns
2) Add Errata
Case
0.5
Specification Read(all)
Relaxed
value
Except for
ID Read
ID Read
1) Change AC characteristics
tDH
Before
0.6
After
2) Add tADL parameter
- tADL=100ns
3) Correct table.9
1) Correct AC Timing Characteristics Table
- Errata value is eddited.
- tADL(max) is changed to tADL(min).
2) Change Errata
- tREA is deleted from the errata
Case
Before
After
Except for
ID Read
ID Read
0.7
Read (all)
tRC
50
60
60
tRP
20
25
25
tREH
20
30
30
Apr. 06. 2005
Preliminary
10
15
Mar. 09. 2005
Preliminary
tRC
50
50
60
tRP
20
20
25
tREH
20
20
30
tREA
30
30
30
Jan. 25. 2005
Preliminary
- Continued -
Draft Date
Remark
3) Edit pin Description table
4) Delete Multiple Die & Stacked Devices Access
- Texts & tables are deleted.
5) Edit Data Protection texts
6) Add Read ID table
7) Add tOH parameter
- tOH=15ns(min.)
8) Add Marking Information
9) Correct application note.2
- tCS(2us) is changed to 100ns.
Rev 0.7 / Apr. 2005
2
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- Manufacturer Code
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
- Device Code
: HY27UFXX1G2M
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27(U/S)F(08/16)1G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27(U/S)F(08/16)1G2M-T (Lead)
- HY27(U/S)F(08/16)1G2M-TP (Lead Free)
- HY27(U/S)F(08/16)1G2M-V(P)
: 48-Pin WSOP1 (12 x 17 x 0.7 mm)
- HY27(U/S)F(08/16)1G2M-V (Lead)
- HY27(U/S)F(08/16)1G2M-VP (Lead Free)
- HY27(U/S)F(08/16)1G2M-F(P)
: 63-Ball FBGA (9.5 x 12 x 1.0 mm)
- HY27(U/S)F(08/16)1G2M-F (Lead)
- HY27(U/S)F(08/16)1G2M-FP (Lead Free)
- 1.8V device: VCC = 1.7 to 1.95V : HY27SFXX1G2M
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 1,024 Blocks
= (1K+32) Words x 64 pages x 1,024 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27(U/S)F081G2M
- x16 device: (1K + 32 spare) Words
: HY27(U/S)F161G2M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 27us
(1)
(max.)
- Sequential access: 60ns
(1)
(min.)
- Page program time: 300us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
NOTE:
1. These parameters are applied to the errata.
Rev 0.7 / Apr. 2005
3
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27(U/S)F(08/16)1G2M series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 1.8V
Vcc Power Supply and in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 60ns
(1)
cycle time per word. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP# input pin.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-
tiple memories the RB# pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27(U/S)F(08/16)1G2M extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the
code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-
tion.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension.
The HYNIX HY27(U/S)F(08/16)1G2M series is available in 48 - TSOP1 12 x 20 mm , 48 - WSOP1 12 x 17 mm,
FBGA 9.5 x 12 mm.
1.1 Product List
PART NUMBER
HY27SF081G2M
HY27SF161G2M
HY27UF081G2M
HY27UF161G2M
ORIZATION
x8
x16
x8
x16
VCC RANGE
1.70 - 1.95 Volt
63FBGA / 48TSOP1 / 48WSOP1
2.7V - 3.6 Volt
PACKAGE
NOTE:
1. This parameters is applied to the errata.
Rev 0.7 / Apr. 2005
4
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE#
RE#
WE#
WP#
RB#
Vcc
Vss
NC
PRE
Data Input / Outputs (x16 only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Power-On Read Enable
Table 1: Signal Names
Rev 0.7 / Apr. 2005
5
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