EN5364QI
Feature Rich 6A Voltage Mode
Synchronous Buck PWM DC-DC Converter
with Integrated Inductor
RoHS Compliant - Halogen Free
Description
The EN5364QI is a Power Supply on a Chip
(PwrSoC) DC to DC converter with integrated
inductor, PWM controller, MOSFETS, and
compensation providing the smallest possible
solution size in a 68 pin QFN module. The
switching frequency can be synchronized to an
external clock or other EN5364QIs with the
added capability of phasing multiple EN5364QIs
as desired. Other features include precision
ENABLE threshold, pre-bias monotonic start-up,
margining, and parallel operation.
EN5364QI is specifically designed to meet the
precise voltage and fast transient requirements
of present and future high-performance
applications such as set-top boxes/HD DVRs,
LAN/SAN adapter cards, audio/video equipment,
optical networking, multi-function printers, test
and measurement, embedded computing,
storage,
and
servers.
Advanced
circuit
techniques, ultra high switching frequency, and
very advanced, high-density, integrated circuit
and proprietary inductor technology deliver high-
quality, ultra compact, non-isolated DC-DC
conversion. Operating this converter requires
very few external components.
The Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity
by offering greatly simplified board design, layout
and manufacturing requirements.
All Enpirion products are RoHS compliant and
lead-free manufacturing environment compatible.
Typical Application Circuit
V
IN
47μF
PVIN
AVIN
ENABLE
PGND
SS
VFB
VOUT
V
OUT
47μF
15nF
PGND
AGND
Figure 1: Typical Application Schematic
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated Inductor, MOSFETS, Controller in
a 8 x 11 x 1.85mm package
Wide input voltage range of 2.375V to 6.6V.
> 20W continuous output power.
High efficiency, up to 93%.
Output voltage margining
Monotonic output voltage ramp during start-
up with pre-biased loads.
Precision Enable pin for accurate sequencing
of power converters and Power OK signal.
Programmable soft-start time.
Soft Shutdown.
4 MHz operating frequency with ability to
synchronize to an external system clock or
other EN5364’s.
Programmable phase delays between
synchronized units to allow reduction of
input ripple.
Master/slave configuration for paralleling
multiple EN5364’s for greater power output.
Under Voltage Lockout, Over-current, Short
Circuit, and Thermal Protection
RoHS compliant, MSL level 3, 260C reflow.
©Enpirion
2009 all rights reserved, E&OE
03544
1
8/21/2009
www.enpirion.com
Rev:B
EN5364QI
Applications
•
•
•
•
•
Point of load regulation for low-power
processors, network processors, DSPs,
FPGAs, and ASICs
Low voltage, distributed power architectures
with 2.5V, 3.3V or 5V, 6V rails
Computing, broadband, networking,
LAN/WAN, optical, test & measurement
A/V, high density cards, storage, DSL, STB,
DVR, DTV, Industrial PC
Beat frequency sensitive applications
•
•
•
Applications requiring monotonic start-up with
pre-bias
Ripple voltage sensitive applications
Noise sensitive applications
Ordering Information
Part Number
EN5364QI-T
EN5364QI-E
Temp Rating
Package
(°C)
-40 to +85
68-pin QFN T&R
QFN Evaluation Board
Pin Configuration
Figure 2: Pinout Diagram (Top View). All perimeter pins must be soldered to PCB.
©Enpirion
2009 all rights reserved, E&OE
03544
2
8/21/2009
www.enpirion.com
Rev:B
EN5364QI
Pin Descriptions
PIN
1-4,
27-33,
64-68
5-13
14-24,
44-47
25-26
34-43
48
49
50
51
52
53
54
55
56
57
58
59
60
61-62
63
69, 70
NAME
PGND
VOUT
NC
FUNCTION
Input/Output power ground. Connect these pins to the ground electrode of the input
and output filter capacitors. See VOUT and PVIN descriptions for more details.
Regulated converter output. Connect to the load, and place output filter capacitor(s)
between these pins and PGND pins 1-4 and 64-68.
NO CONNECT: These pins must be soldered to PCB but not be electrically connected
to each other or to any external signal, voltage, or ground. These pins may be
connected internally. Failure to follow this guideline may result in device damage.
NO CONNECT: These pins are internally connected to the common switching node of
the internal MOSFETs. They must be soldered to PCB but not be electrically
connected to any external signal, ground, or voltage. Failure to follow this guideline
may result in device damage.
Input power supply. Connect to input power supply, place input filter capacitor(s)
between these pins and PGND pins 27-33.
Clock Output. Depending on the mode, either a clock signal or the PWM signal is
output on this pin. These signals are delayed by a time that is related to the resistor
connected between S_DELAY and AGND. Leave this pin floating if not needed.
Clock Input. Depending on the mode, this pin accepts either an input clock to
synchronize the internal switching frequency or the S_OUT signal from another
EN5364QI. Leave this pin floating if it is not used.
This is a Ternary Input. Floating the pin disables parallel operation. A low level
configures the device as Master and a High level configures the device as a slave.
This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support
monotonic start-up under a pre-biased load. There is a 150kΩ pull-down on this pin.
This is the Device Enable pin. A high level enables the device while a low level
disables the device.
Input power supply for the controller. Needs to be connected to V
IN
at a quiet point.
Power OK is an open drain transistor for power system state indication. POK is a
logic high when VOUT is with -10% to +20% of VOUT nominal. Being an open drain
output allows several devices to be wired to logically AND the function. Size pull-up
resistor to limit current to 4mA when POK is low.
Ground return for the controller. Needs to be connected to a quiet ground.
External Feedback input. The feedback loop is closed through this pin. A voltage
divider at V
OUT
is used to set the output voltage. The mid-point of the divider is
connected to VFB. The control loop regulates to make the VFB node voltage 0.6V.
Optional Error Amplifier output. Allows for customization of the control loop.
When this pin is pulled to AGND, the overcurrent protection trip point is increased by
approximately 30%. Leave floating for default OCP threshold (see Electrical
Characteristics table). Tie this pin to AGND for pin compatibility with the EN5394.
A soft-start capacitor is connected between this pin to AGND. The value of the
capacitor controls the soft-start interval and startup time.
A resistor is connected between this pin and AGND. The value of the resistor controls
the delay in S_OUT. This pin can be left floating if the S_OUT function is not used.
These are 2 ternary input pins. Each pin can be a logical Lo, Logical Hi or Float
condition. 7 of the 9 states are used to modulate the output voltage by 0%, ±2.5%,
±5% or ±10%. The 8th state is used to by-pass the delay in S_OUT. See Functional
Description section.
This pin senses VOUT when the device is placed in the Back-feed (or Pre-bias) mode.
Device thermal pads to be connected to the system gnd plane. See Layout
Recommendations section.
3
8/21/2009
NC(SW)
PVIN
S_OUT
S_IN
M/S
EN_PB
ENABLE
AVIN
POK
AGND
VFB
EAOUT
OCP_ADJ
SS
S_DELAY
MAR1,
MAR2
VSENSE
PGND
©Enpirion
2009 all rights reserved, E&OE
03544
www.enpirion.com
Rev:B
EN5364QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
Voltages on PVIN, AVIN, VOUT
Voltages on VSENSE, ENABLE, EN_PB, POK,
Voltages on VFB, EAOUT, SS, S_IN, S_OUT, OCP_ADJ
Voltages on MAR1, MAR2, M/S
Storage Temperature Range
Maximum Operating Junction Temperature
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
SYMBOL
V
IN
MIN
-0.5
-0.5
-0.5
-0.5
-65
MAX
7.0
V
IN
+ 0.3
2.7
3.6
150
150
260
2000
UNITS
V
V
V
V
°C
°C
°C
V
T
STG
T
J-ABS MAX
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
V
IN
2.375
6.6
V
†
Output Voltage Range
V
OUT
0.60
V
IN
– V
DO
V
Output Current
I
LOAD
0
6
A
Operating Ambient Temperature
T
A
-40
+85
°C
Operating Junction Temperature
T
J
-40
+125
°C
†
V
DO (
drop-out voltage) is defined as (I
LOAD
x Dropout Resistance). Please see Electrical Characteristics table.
Thermal Characteristics
PARAMETER
††
SYMBOL
TYP
UNITS
°C/W
°C/W
°C
°C
Thermal Resistance: Junction to Ambient (0 LFM)
θ
JA
16
Thermal Resistance: Junction to Case
θ
JC
1
Thermal Shutdown Trip Point
T
SD
+150
Thermal Shutdown Trip Point Hysteresis
T
SDH
20
††
Based on a four-layer board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards.
©Enpirion
2009 all rights reserved, E&OE
03544
4
8/21/2009
www.enpirion.com
Rev:B
EN5364QI
Electrical Characteristics
NOTE: V
IN
=5.5V over operating temperature range unless otherwise noted.
Typical values are at T
A
= 25°C.
PARAMETER
Input Voltage
Under Voltage Lock out
threshold
Shut-Down Supply
Current
Feedback Pin Voltage
Feedback Pin Input Leakage
Current
1
SYMBOL
V
IN
V
UVLOR
V
UVLOF
I
S
V
FB
I
FB
ΔV
OUT_LINE
ΔV
OUT_LOAD
ΔV
OUT_TEMP
T
RISE
ΔT
RISE
V
DO
R
DO
I
OUT_MAX_CONT
COMMENTS
V
IN
Increasing
V
IN
Decreasing
ENABLE=0V
2.375V
≤
VIN
≤
6.6V,
I
LOAD
= 1A; T
A
= 25°C
2.375V
≤
V
IN
≤
6.6V
0A
≤
ILOAD
≤
6A
-40°C
≤
TEMP
≤
85°C
Measured from when V
IN
≥
V
UVLOR
& ENABLE pin crosses logic high
threshold. (4.7nF
≤
C
SS
≤
100nF)
4.7nF
≤
C
SS
≤
100nF
V
INMIN
– V
OUT
at Full Load
Input to Output Resistance
MIN
2.375
TYP
2.2
2.1
250
MAX
6.6
UNITS
V
V
μA
0.588
-5
0.600
0.612
5
V
nA
%/V
%/A
%/°C
Line Regulation
Load Regulation
Temperature Regulation
V
OUT
Rise Time
Rise Time Accuracy
1
Output Dropout
Voltage
1
Resistance
1
Maximum Continuous
Output Current
2
Current Limit Threshold
ENABLE pin:
Disable Threshold
Enable Threshold
ENABLE Lock-out time
ENABLE Pin Input
Current
Switching Frequency
External S_IN Clock
Frequency Lock Range
S_IN Threshold – Low
S_IN Threshold – High
S_OUT Threshold – Low
S_OUT Threshold – High
S_IN Duty Cycle for
External Synchronization
1
S_IN Duty Cycle for
Parallel Operation
1
Phase Delay vs. S_Delay
Resistor value
Phase Delay between
S_IN and S_OUT
1
0.035
−0.04
0.001
C
SS
x
65kΩ
-25
240
40
6
+25
480
80
%
mV
mΩ
A
A
I
OCP
V
DISABLE
V
ENABLE
t
ENLO
OCP_ADJ floating
2.375V
≤
V
IN
≤
6.6V
ENABLE pin logic low
ENABLE pin logic high
Time for device to re-enable after
a falling edge on ENABLE pin
V
IN
= 5.5V
Free Running frequency
Frequency Range of S_IN
Input Clock
S_IN Clock low level
S_IN Clock high level
S_OUT Clock low level
S_OUT Clock high level
M/S Pin Float or Low
M/S Pin High
Delay in ns / kΩ
Delay in phase angle / kΩ -
@ 4MHz switching frequency
Phase delay programmable via
resistor connected from S_Delay
to AGND.
5
8/21/2009
10.5
1.10
2
50
4
3.6
1.8
1.8
20
10
2
3
20
150
80
90
4.4
0.8
2.5
0.5
1.0
1.30
V
ms
μA
MHz
MHz
V
V
V
V
%
%
ns
°
ns
I
ENABLE
F
SWITCH
F
PLL_LOCK
V
S_IN_LO
V
S_IN_HI
V
S_OUT_LO
V
S_OUT_HI
SY
DC_SYNC
SY
DC_PWM
Φ
DEL
Φ
DEL
©Enpirion
2009 all rights reserved, E&OE
03544
www.enpirion.com
Rev:B
京公网安备 11010802033920号
EEWORLD
