EN5310
ENPIRION
Description
1A Voltage Mode Synchronous Buck PWM
DC-DC Converter
Features
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•
•
•
•
•
•
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1000mA output current capacity
External inductor is NOT required
Lead-Free packaging
5MHz operating frequency
More than 90% efficient
V
OUT
accuracy of 2% over line, load and
temperature
1/2 the board area of discrete component solutions
Very fast transient response
All high speed switching signals contained inside
the part
Wide input voltage range of 2.375V to 5.5V
Digital voltage selector with options for common
output voltages from 0.8V to 3.3V
External resistor divider and OVP option for
programming output voltages from 0.9V to 4.0V
Output enable pin and Power OK signal
Programmable soft-start time
Programmable over-current protection
Thermal shutdown, short circuit, over-voltage and
under-voltage protection
The EN5310 is a Power System on a Chip DC-DC
converter. It is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in a distributed power architecture.
Advanced circuit techniques, ultra high switching
frequency, and very advanced, high-density,
integrated circuit and proprietary inductor technology
deliver high-quality, ultra compact, non-isolated DC-
DC conversion. Operating this converter requires only
three external components that include small value
input and output ceramic capacitors and a soft-start
capacitor.
The EN5310 significantly helps in system design and
productivity by offering greatly simplified board
design, layout and manufacturing requirements. In
addition, a reduction in the number of vendors
required for the complete power solution helps to
enable an overall system cost savings.
Applications
Typical Application Circuit
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•
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V
IN
10µF
PVIN
AVIN
VS0
VS1
VS2
VID Output
Voltage Select
•
POK
SS
VOIP phones, video telephones
Broadband, networking, LAN/WAN, optical
telecommunications equipment
Point of load regulation for low-power processors,
network processors, DSPs, FPGAs, and ASICs
Low voltage, distributed power architectures with
2.5V, 3.3V or 5V rails
VSENSE
VOUT
V
OUT
22µF
Ordering Information
Part Number
EN5310DC
EN5310DC-T
EN5310DI
EN5310DI-T
EN5310DC-E
Temp Rating (°C)
Package
0 to 70
36-pin DFN
0 to 70
36-pin DFN T&R
-40 to +85
36-pin DFN
-40 to +85
36-pin DFN T&R
DFN Evaluation Board
15nF
AGND
PGND
Rev 0.95 – March 2005
1
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Rev 0.95 – March 2005
EN5310
Pin Configuration
This diagram is a top-view of the component and represents the on-board layout requirements for the
landing pads and thermal connection points. Specific dimensions for the pads are presented on page 10.
Pin 1 of the device is signified by the white dot marked on the top of the device.
Block Diagram
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Rev 0.95 – March 2005
EN5310
Typical Efficiency
V
IN
= 3.3V and V
OUT
= 2.5V
100%
90%
80%
70%
60%
50%
40%
0
200
400
600
800
1000
1200
Output Current (mA)
Absolute Maximum Ratings
CAUTION: Stresses in excess of the absolute maximum ratings can cause permanent damage to the device.
Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
PARAMETER
Input Supply Voltage
Input Voltage – Enable
Input Voltage – VS0, VS1 & VS2
(Note 1)
Storage Temperature Range
Operating Junction Temperature
MSL per JEDEC J-STD-020A Level 3
(Note 2)
ESD Rating (based on Human Body Model)
NOTES:
1.
2.
SYMBOL
V
IN
T
STG
T
J
MIN
-0.5
-0.5
-0.5
-65
MAX
6.5
V
IN
2.8
150
150
240
2000
UNITS
V
V
V
°C
°C
°C
V
VS0, VS1 and VS2 pins have an internal pull-up resistor, only ground potentials should be placed on them as required.
Evaluation for MSL3 at 255°C in process.
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM)
(Note 3)
Thermal Resistance: Junction to Case (0 LFM)
NOTES:
3.
Based on a four-layer board and proper thermal design.
SYMBOL
θ
JA
θ
JC
TYPICAL
36
6
UNITS
°C/W
°C/W
3
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Rev 0.95 – March 2005
EN5310
Electrical Characteristics
NOTE: V
IN
=3.3V and over operating temperature range unless otherwise noted. Typical values are at T
A
=
25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Operating Input
V
IN
2.375
Voltage
Quiescent Supply
No switching, AVIN = 3.3V,
I
Q
PVIN = 3.3V, ENABLE=0V
Current
No-Load Operating
Includes PWM, gate drive and
I
NL
Current
inductor ripple current.
Switching
F
OSC
Frequency
Thermal Overload
T
J
Trip Point
V
OUT
Range
V
OUT
Using external voltage divider
0.9
Accuracy
V
OUT
Over line, load and temperature
Line Regulation
V
IN
= 2.5 to 5.0 volts
∆V
OUT
Load Regulation
I
LOAD
= 0 to 1A
∆V
OUT
T
A
= 0 to 70ºC
Temperature
∆V
OUT
Regulation
T
A
= -40 to 85ºC
∆V
OUT
Transient Response (I
OUT
= 0% to 100% or 100% to 0% of Rated Load)
Peak Deviation
V
OUT
V
IN
= 5V, 1.2V < V
OUT
< 3.3V
Output Voltage Ripple
V
IN
= 5.0V, V
OUT
= 1.2V, I
OUT
= 1A,
Peak-to-peak
V
OUT-PP
C
OUT
= 20uF, 2 x 10µF X5R or X7R
ceramic capacitors
Maximum Continuous Output Current (Note 4)
Output Current
I
OUT
Enable Operation
Max voltage to ensure the converter
Disable Threshold
V
DISABLE
is disabled
Min voltage to ensure the converter
1.8
Enable Threshold
V
ENABLE
is enabled
Power OK Operation
POK low voltage
V
POK
I
POK
= 1mA
Max POK Voltage
V
POK
Supply voltage applied to POK
NOTES:
4.
TYP
MAX
5.5
UNITS
V
mA
mA
MHz
°C
V
%
mV
mV
mV
mV
%
mV
15
35
5
160
2.0
3
3
TBD
TBD
2
12
1000
0.8
5
mA
V
V
0.4
5.5
V
V
Maximum output current may need to be de-rated, based on operating condition, to meet T
J
requirements.
4
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Rev 0.95 – March 2005
EN5310
FUNCTION
NO CONNECT – Do not electrically connect this pin to PCB.
See Note 5.
External feedback voltage input. Option for programming the output voltage with a
resistor divider on V
OUT
.
Remote voltage sense input. Connect this pin to the load voltage at the point to be
regulated.
NO CONNECT – Do not electrically connect this pin to PCB.
See Note 5.
NO CONNECT – Do not electrically connect this pin to PCB.
See Note 5.
Enable input. An input high enables operation. An input low disables operation.
NO CONNECT – Do not electrically connect this pin to PCB.
See Note 5.
Over-Voltage set-point input. When using an external voltage divider and the XFB pin. When
VS0, VS1 and VS2 are left OPEN or pulled high, an additional voltage divider separate from
the XFB pin is required to set the OVP set-point. In this mode, the OVP function is disabled if
this voltage divider is not present.
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NOTES:
5.
NAME
NC
XFB
VSENSE
NC
NC
ENABLE
NC
XOV
PGND
Power ground for the power stage circuits.
VOUT
Voltage and power output.
NC
PGND
NC
PVIN
VS2
ROCP
VS1
AVIN
AGND
VS0
POK
SS
NO CONNECT – Do not electrically connect this pin to PCB.
See Note 5.
Power ground for the power stage circuits.
NO CONNECT – Do not electrically connect this pin to PCB.
See Note 5.
Power voltage input for the power stage circuits.
Voltage select line 2 input. See Table 1.
Over-Current trip point adjust input. Used for adjusting the OCP trip point.
Voltage select line 1 input. See Table 1.
Analog voltage input for the controller circuits.
Analog ground for the controller circuits.
Voltage select line 0 input. See Table 1.
Power OK is an open drain transistor for power system state indication.
Soft-Start node. A capacitor is connected between this pin and AGND.
This pin is used for engineering test purposes and reserved for future use. Solder, but do not electrically connect this pin to
the PCB.
5
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