TMC2330AKEC datasheet, PDF - EEWORLD Datasheet

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TMC2330AKEC: Descriptioncoordinate transformer 16 x 16 bit, 40 mops; CategoryThe embedded processor and controller Microcontrollers and processors; File Size162KB，18 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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TMC2330AKEC Overview

coordinate transformer 16 x 16 bit, 40 mops

TMC2330AKEC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
package instruction	QFP,
Reach Compliance Code	compliant
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	32
JESD-30 code	S-PQFP-G120
JESD-609 code	e0
length	28 mm
low power mode	NO
Number of terminals	120
Maximum operating temperature	70 °C
Minimum operating temperature
Output data bus width	16
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.92 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	28 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR

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www.fairchildsemi.com

TMC2330A

Coordinate Transformer

16 x 16 Bit, 40 MOPS

Features

• Rectangular-to-Polar or Polar-to-Rectangular conversion

at guaranteed 40 MOPS pipelined throughput rate

• Polar data: 16-bit magnitude, 32-bit input/16-bit output

phase

• 16-bit user selectable two’s complement or sign-and-

magnitude rectangular data formats

• Input register clock enables and asynchronous output

enables simplify interfacing

• User-conﬁgurable phase accumulator for waveform

synthesis and amplitude, frequency, or phase modulation

• Magnitude output data overﬂow ﬂag (in Polar-to-

Rectangular mode)

• Low power consumption CMOS process

• Single +5V power supply

• Available in a 120-pin plastic pin grid array package

(PPGA), 120-pin ceramic pin grid array package (CPGA),

120-pin MQFP to PPGA (MPGA) package, and 120-pin

metric quad ﬂatpack package (MQFP)

Description

The TMC2330A VLSI circuit converts bidirectionally

between Cartesian (real and imaginary) and Polar (magnitude

and phase) coordinates at up to 40 MOPS (Million Operations

Per Second).

In its Rectangular-to-Polar mode, the TMC2330A can extract

phase and magnitude information or backward “map” from a

rectangular raster display to a radial (e.g., range-and-azimuth)

data set.

The Polar-to-Rectangular mode executes direct digital waveform

synthesis and modulation. The TMC2330A greatly simpliﬁes

real-time image-space conversion between the radially-generated

image scan data found in radar, sonar, and medical imaging

systems, and raster display formats.

All input and output data ports are registered, and a new trans-

formed data word pair is available at the output every clock

cycle. The user-conﬁgurable phase accumulator structure,

input clock enables, and asynchronous three-state output bus

enables simplify interfacing. All signals are TTL compatible.

Fabricated in a submicron CMOS process, the TMC2330A

operates at up to the 40 MHz maximum clock rate over the full

commercial (0 to 70°C) temperature and supply voltage ranges,

and is available in 120-pin plastic pin grid array, 120-pin

ceramic pin grid array, 120-pin metric quad ﬂatpack to PPGA

package, and 120-pin metric quad ﬂatpack packages.

Applications

•

Scan conversion (phased array to raster)

Vector magnitude estimation

Range and bearing derivation

Spectral analysis

Digital waveform synthesis, including quadrature

functions

• Digital modulation and demodulation

Logic Symbol

ENXR

XRIN

15-0

DATA

INPUTS

ENYP

1-0

YPIN

31-0

OEPY

ACC

1-0

CONFIGURATION

CONTROLS

TCXY

RTP

CLK

OVF

PYOUT

15-0

RXOUT

15-0

DATA

OUTPUTS

OERX

TMC2330A

REV. 1.1.8 10/31/00

TMC2330AKEC Related Products

	TMC2330AKEC	TMC2330AKEC1	TMC2330AH6C1	TMC2330AH6C
Description	coordinate transformer 16 x 16 bit, 40 mops	coordinate transformer 16 x 16 bit, 40 mops	coordinate transformer 16 x 16 bit, 40 mops	coordinate transformer 16 x 16 bit, 40 mops
Is it Rohs certified?	incompatible	-	incompatible	incompatible
Maker	Fairchild	-	Fairchild	Fairchild
package instruction	QFP,	-	PGA,	PGA,
Reach Compliance Code	compliant	-	compliant	compliant
boundary scan	NO	-	NO	NO
maximum clock frequency	20 MHz	-	40 MHz	20 MHz
External data bus width	32	-	32	32
JESD-30 code	S-PQFP-G120	-	S-CPGA-P120	S-CPGA-P120
length	28 mm	-	34.545 mm	34.545 mm
low power mode	NO	-	NO	NO
Number of terminals	120	-	120	120
Maximum operating temperature	70 °C	-	70 °C	70 °C
Output data bus width	16	-	16	16
Package body material	PLASTIC/EPOXY	-	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFP	-	PGA	PGA
Package shape	SQUARE	-	SQUARE	SQUARE
Package form	FLATPACK	-	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	3.92 mm	-	9.17 mm	9.17 mm
Maximum supply voltage	5.25 V	-	5.25 V	5.25 V
Minimum supply voltage	4.75 V	-	4.75 V	4.75 V
Nominal supply voltage	5 V	-	5 V	5 V
surface mount	YES	-	NO	NO
technology	CMOS	-	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	-	PIN/PEG	PIN/PEG
Terminal pitch	0.8 mm	-	2.54 mm	2.54 mm
Terminal location	QUAD	-	PERPENDICULAR	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	28 mm	-	34.545 mm	34.545 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR	-	DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR	DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR

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