PRELIMINARY
Am186 EM/EMLV and Am188 EM/EMLV
TM
TM
High Performance, 80C186-/80C188-Compatible and
80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers
DISTINCTIVE CHARACTERISTICS
n
E86
TM
family 80C186- and 80C188-compatible
microcontrollers with enhanced bus interface
— Lower system cost with higher performance
— 3.3- V ±.3 -V ope ra tio n (A m1 86E MLV and
Am188EMLV microcontrollers)
n
High performance
— 20-, 25-, 33-, and 40-MHz operating frequencies
— Supports zero-wait-state operation at 25 MHz
with 110-ns static memory (Am186
TM
EMLV and
Am188
TM
EMLV microcontrollers) and 40 MHz
with 70-ns static memory (Am186
TM
EM and
Am188
TM
EM microcontrollers)
— 1-Mbyte memory address space
— 64-Kbyte I/O space
n
New features provide faster access to memory and
remove the requirement for a 2x clock input
— Nonmultiplexed address bus
— Phase-locked loop (PLL) allows processor to
operate at the clock input frequency
n
New integrated peripherals provide increased
functionality while reducing system cost
— Thirty-two programmable I/O (PIO) pins
— Asynchronous serial port allows full-duplex, 7-bit
or 8-bit data transfers
— Synchronous serial interface allows half-duplex,
bidirectional data transfer to and from ASICs
— Pseudo static RAM (PSRAM) controller includes
auto refresh capability
— Reset configuration register
Familiar 80C186/80L186 peripherals
— Two independent DMA channels
— Programmable interrupt controller with six
external interrupts
— Three programmable 16-bit timers—timer 1 can
be used as a watchdog interrupt timer
— Programmable memory and peripheral
chip-select logic
— Programmable wait state generator
— Power-save clock divider
Software-compatible with the 80C186/80C188
and 80L186 /80L188 microcontrollers
Widely available native development tools,
applications, and system software
Available in the following packages:
— 100-pin, thin quad flat pack (TQFP)
— 100-pin, plastic quad flat pack (PQFP)
n
n
n
n
GENERAL DESCRIPTION
The Am186
TM
EM/EMLV and Am188
TM
EM/EMLV micro-
controllers are the ideal upgrade for 80C186/188 and
80L186/188 microcontroller designs requiring 80C186/
188 and 80L186/188 microcontroller compatibility, in-
creased performance, serial communications, and a di-
rect bus interface. The Am186EM/EMLV and
Am188EM/EMLV microcontrollers increase the perfor-
mance of existing 80C186/188 and 80L186/188 sys-
tems while decreasing their cost.
The Am186EM/EMLV and Am188EM/EMLV microcon-
trollers are part of the AMD E86 family of embedded mi-
crocontrollers and microprocessors based on the x86
architecture. The E86 family includes the 16- and 32-bit mi-
crocontrollers and microprocessors described on page 8
The Am186EM/EMLV and Am188EM/EMLV microcon-
trollers integrate the functions of the CPU, nonmulti-
plexed address bus, timers, chip selects, interrupt
controller, DMA controller, PSRAM controller, asynchro-
nous serial port, synchronous serial interface, and pro-
grammable I/O (PIO) pins on one chip. Compared to the
80C186/188 and 80L186/188 microcontrollers, the
Am186EM/EMLV and Am188EM/EMLV microcontrol-
lers enable designers to reduce the size, power con-
sumption, and cost of embedded systems, while
increasing functionality and performance.
The Am186EM/EMLV and Am188EM/EMLV microcon-
trollers have been designed to meet the most common
requirements of embedded products developed for the
office automation, mass storage, communications, and
general embedded markets. Specific applications in-
clude disk drives, hand-held terminals and desktop ter-
minals, fax machines, printers, photocopiers, feature
phones, cellular phones, PBXs, multiplexers, modems,
and industrial controls.
Publication#
19168
Rev:
E
Amendment/0
Issue Date:
February 1997
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
P R E L I M I N A R Y
RD
Read Strobe (output, synchronous, three-state)
This pin indicates to the system that the microcontroller
is performing a memory or I/O read cycle. RD is guar-
anteed not to be asserted before the address and data bus
is floated during the address-to-data transition. RD floats
during a bus hold condition.
RXD/PIO28
Receive Data (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to the internal UART of the microcon-
troller.
S2
–
S0
Bus Cycle Status (output, three-state,
synchronous)
These pins indicate to the system the type of bus cycle
in progress. S2 can be used as a logical memory or I/O
indicator, and S1 can be used as a data transmit or receive
indicator. S2–S0 float during bus hold and hold acknowl-
edge conditions. The S2–S0 pins are encoded as shown
in Table 4.
RES
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller immediately
terminates its present activity, clears its internal logic, and
CPU control is transferred to the reset address FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLKOUTA
because RES is synchronized internally. For proper ini-
tialization, V
CC
must be within specifications, and CLK-
OUTA must be stable for more than four CLKOUTA
periods during which RES is asserted.
The microcontroller begins fetching instructions ap-
proximately 6.5 CLKOUTA periods after RES is deas-
serted. This input is provided with a Schmitt trigger to
facilitate power-on RES generation via an RC network.
Table 4.
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bus Cycle Encoding
Bus Cycle
Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
None (passive)
S0
RFSH2/ADEN
(Am188EM Microcontroller Only)
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Asserted
Low to signify a DRAM refresh bus
cycle. The use of RFSH2/ADEN to signal a refresh is
not valid when PSRAM mode is selected. Instead, the
MCS3/RFSH signal is provided to the PSRAM.
ADEN—If
RFSH2/ADEN is held High or left floating on
power-on reset, the AD bus (AO15–AO8 and AD7–
AD0) is enabled or disabled during the address portion
of LCS and UCS bus cycles based on the DA bit in the
LMCS and UMCS registers. If the DA bit is set, the
memory address is accessed on the A19–A0 pins. This
mode of operation reduces power consumption. For
more information, see the “Bus Operation” section on
page 37. There is a weak internal pullup resistor on
RFSH2/ADEN so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data regardless of the DA
bit setting. The pin is sampled one crystal clock cycle after
the rising edge of RES. RFSH2/ADEN is three-stated
during bus holds and ONCE mode.
S6/CLKDIV2/PIO29
Bus Cycle Status Bit 6 (output, synchronous)
Clock Divide by 2 (input, internal pullup)
S6—During
the second and remaining periods of a
cycle (t
2
, t
3
, and t
4
), this pin is asserted High to indicate
a DMA-initiated bus cycle. During a bus hold or reset
condition, S6 floats.
CLKDIV2—If
S6/CLKDIV2/PIO29 is held Low during
power-on reset, the chip enters clock divided by 2
mode where the processor clock is derived by dividing
the external clock input by 2. If this mode is selected,
the PLL is disabled. The pin is sampled on the rising
edge of RES.
If S6 is to be used as PIO29 in input mode, the device
driving PIO29 must not drive the pin Low during power-
on reset. S6/CLKDIV2/PIO29 defaults to a PIO input with
pullup, so the pin does not need to be driven High exter-
nally.
Am186/188EM and Am186/188EMLV Microcontrollers
31
P R E L I M I N A R Y
SCLK/PIO20
Serial Clock (output, synchronous)
This pin supplies the synchronous serial interface (SSI)
clock to a slave device, allowing transmit and receive
operations to be synchronized between the microcon-
troller and the slave. SCLK is derived from the micro-
controller internal clock and then divided by 2, 4, 8, or
16 depending on register settings.
An access to any of the SSR or SSD registers activates
SCLK for eight SCLK cycles (see Figure 11 and Figure
12 on page 49). When SCLK is inactive, it is held High
by the microcontroller.
TMRIN1/PIO0
Timer Input 1 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 1. After internally synchronizing a
Low-to-High transition on TMRIN1, the microcontroller
increments the timer. TMRIN1 must be tied High if not
being used.
TMROUT0/PIO10
Timer Output 0 (output, synchronous)
This pin supplies the system with either a single pulse
or a continuous waveform with a programmable duty
cycle. TMROUT0 is floated during a bus hold or reset.
SDATA/PIO21
Serial Data (input/output, synchronous)
This pin transmits synchronous serial interface (SSI)
data to and from a slave device. When SDATA is inac-
tive, a weak keeper holds the last value of SDATA on
the pin.
TMROUT1/PIO1
Timer Output 1 (output, synchronous)
This pin supplies the system with either a single pulse
or a continuous waveform with a programmable duty
cycle. TMROUT1 can also be programmed as a watch-
dog timer. TMROUT1 is floated during a bus hold or re-
set.
SDEN1/PIO23, SDEN0/PIO22
Serial Data Enables (output, synchronous)
These pins enable data transfers on port 1 and port 0
of the synchronous serial interface (SSI). The micro-
controller asserts either SDEN1 or SDEN0 at the be-
ginning of a transfer and deasserts it after the transfer
is complete. When SDEN1–SDEN0 are inactive, they
are held Low by the microcontroller.
TXD/PIO27
Transmit Data (output, asynchronous)
This pin supplies asynchronous serial transmit data to
the system from the internal UART of the microcontrol-
ler.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
UCS—This
pin indicates to the system that a memory
access is in progress to the upper memory block. The
base address and size of the upper memory block are
programmable up to 512 Kbytes. UCS is held High dur-
ing a bus hold condition.
After power-on reset, UCS is asserted because the pro-
cessor begins executing at FFFF0h and the default config-
uration for the UCS chip select is 64 Kbytes from F0000h
to FFFFFh.
ONCE1—During
reset, this pin and ONCE0 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode. Otherwise, it operates normally. In
ONCE mode, all pins assume a high-impedance state
and remain in that state until a subsequent reset oc-
curs. To guarantee that the microcontroller does not in-
advertently enter ONCE mode, ONCE1 has a weak
internal pullup resistor that is active only during a reset.
This pin is not three-stated during a bus hold condition.
SRDY/PIO6
Synchronous Ready (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that the ad-
dressed memory space or I/O device will complete a
data transfer. The SRDY pin accepts an active High
input synchronized to CLKOUTA.
Using SRDY instead of ARDY allows a relaxed system
timing because of the elimination of the one-half clock
period required to internally synchronize ARDY. To al-
ways assert the ready condition to the microcontroller,
tie SRDY High. If the system does not use SRDY, tie
the pin Low to yield control to ARDY.
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 0. After internally synchronizing a
Low-to-High transition on TMRIN0, the microcontroller
increments the timer. TMRIN0 must be tied High if not
being used.
32
Am186/188EM and Am186/188EMLV Microcontrollers
P R E L I M I N A R Y
UZI/PIO26
Upper Zero Indicate (output, synchronous)
UZI—This pin lets the designer determine if an access
to the interrupt vector table is in progress by ORing it
with bits 15–10 of the address and data bus (AD15–
AD10 on the 186 and AO15–AO10 on the 188). UZI is
the logical OR of the inverted A19–A16 bits, and it as-
serts in the first period of a bus cycle and is held
throughout the cycle.
This signal should be pulled High or allowed to float at
reset. If this pin is Low at the negation of reset, the
Am186EM and Am188EM microcontrollers will enter a re-
served clock test mode.
X1
Crystal Input (input)
This pin and the X2 pin provide connections for a fun-
damental mode or third-overtone parallel-resonant
crystal used by the internal oscillator circuit. To provide
the microcontroller with an external clock source, con-
nect the source to the X1 pin and leave the X2 pin un-
connected.
X2
Crystal Output (output)
This pin and the X1 pin provide connections for a fun-
damental mode or third-overtone parallel-resonant
crystal used by the internal oscillator circuit. To provide
the microcontroller with an external clock source, leave
the X2 pin unconnected and connect the source to the
X1 pin.
V
CC
Power Supply (input)
These pins supply power (+5 V) to the microcontroller.
WHB (Am186EM Microcontroller Only)
Write High Byte (output, three-state, synchronous)
This pin and WLB indicate to the system which bytes of
the data bus (upper, lower, or both) participate in a write
cycle. In 80C186 designs, this information is provided by
BHE, AD0, and WR. However, by using WHB and WLB,
the standard system interface logic and external address
latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical
OR of BHE and WR. This pin floats during reset.
WLB (Am186EM Microcontroller Only)
WB (Am188EM Microcontroller Only)
Write Low Byte (output, three-state, synchronous)
Write Byte (output, three-state, synchronous)
WLB—This
pin and WHB indicate to the system which
bytes of the data bus (upper, lower, or both) participate
in a write cycle. In 80C186 designs, this information is
provided by BHE, AD0, and WR. However, by using
WHB and WLB, the standard system interface logic
and external address latch that were required are elim-
inated.
WLB is asserted with AD7–AD0. WLB is the logical OR
of AD0 and WR. This pin floats during reset.
WB—On
the Am188EM microcontroller, this pin indi-
cates a write to the bus. WB uses the same early timing
as the nonmultiplexed address bus. WB is associated
with AD7–AD0. This pin floats during reset.
WR
Write Strobe (output, synchronous)
This pin indicates to the system that the data on the bus
is to be written to a memory or I/O device. WR floats
during a bus hold or reset condition.
Am186/188EM and Am186/188EMLV Microcontrollers
33
P R E L I M I N A R Y
FUNCTIONAL DESCRIPTION
AMD’s Am186 and Am188 family of microcontrollers
and microprocessors is based on the architecture of
the original 8086 and 8088 microcontrollers and cur-
rently includes the 80C186, 80C188, 80L186, 80L188,
Am186EM, Am188EM, Am186EMLV, Am188EMLV,
Am186ES, Am188ES, Am186ESLV, Am188ESLV,
Am186ER, and Am188ER microcontrollers.
All family members contain the same basic set of
registers, instructions, and addressing modes and are
compatible with the industry-standard 80C186/188
microcontrollers.
A full description of all the Am186EM and Am188EM
microcontroller registers is included in the
Am186EM
and Am188EM Microcontrollers User’s Manual
, order#
19713. The instruction set for the Am186EM and
Am188EM microcontrollers is documented in the
Am186
and Am188 Family Instruction Set Manual
, order# 21267.
1
19
0
0
15
2
0
2
2
A
Shift
Left
4 Bits
1
15
0
15
2
A
0
2
4 Segment
Logical
0 Base
Address
Offset
2
0
4
0
0
2
0
2
0
Physical Address
1
19
A
6
To Memory
Memory Organization
Memory is organized in sets of segments. Each seg-
ment is a linear contiguous sequence of 64K (2
16
) 8-bit
bytes. Memory is addressed using a two-component
address that consists of a 16-bit segment value and a
16-bit offset. The 16-bit segment values are contained
in one of four internal segment registers (CS, DS, SS,
or ES). The physical address is calculated by shifting
the segment value left by 4 bits and adding the 16-bit
offset value to yield a 20-bit physical address (see Figure 3).
This allows for a 1-Mbyte physical address size.
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For speed and compact instruction encoding, the seg-
ment register used for physical address generation is
implied by the addressing mode used (see Table 5).
Figure 2. Two-Component Address
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN, INS and OUT, OUTS) ad-
dress the I/O space with either an 8-bit port address
specified in the instruction, or a 16-bit port address in
the DX register. Eight-bit port addresses are zero-ex-
tended so that A15–A8 are Low. I/O port addresses
00F8h through 00FFh are reserved. The Am186EM
and Am188EM microcontrollers provide specific in-
structions for addressing I/O space.
Table 5.
Memory Reference
Needed
Instructions
Local Data
Stack
External Data (Global)
Segment Register Selection Rules
Implicit Segment Selection Rule
Instructions (including immediate data)
All data references
All stack pushes and pops;
any memory references that use BP Register
All string instruction references that use the DI Register as an index
Segment Register
Used
Code (CS)
Data (DS)
Stack (SS)
Extra (ES)
34
Am186/188EM and Am186/188EMLV Microcontrollers
京公网安备 11010802033920号
EEWORLD
