SL74HC4094
8-Bit Serial-Input Shift Register With Latched
3-State Outputs
High-Performance Silicon-Gate CMOS
The SL74HC4094 is identical in pinout to the LS/ALS4094. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of an 8-bit shift register and 8-bit D-type latch
with three-state parallel outputs. Data is shifted serially through the
shift register on the positive going transition of the clock input signal.
The output of the last stage SQ
H
can be used to cascade several
devices.
Data on the SQ
H
output is transferred to a second output (SQ
H
’) on
the following negative transition of the clock input signal. The data of
each stage of the shift register is provided with a latch, which latches
data on the negative going transition of the Strobe input signal. When
the Strobe input is held high, data propagates through the latch to a 3-
state output buffer.
This buffer is enabled when Output Enable input is taken high.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC4094N Plastic
SL74HC4094D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock Output
Enable
PIN 16 =V
CC
PIN 8 = GND
L
L
H
H
H
H
NC = No Change
Z = high impedance
X = don’t care
System Logic
Semiconductor
Parallel
Outputs
Strobe
X
X
L
H
H
X
A
X
X
Q
A
Z
Z
Q
N
Z
Z
NC
Q
N-1
Q
N-1
NC
Serial
Outputs
SQ
H
SQ
H
’
Q6
NC
NC SQ
H
Q6
Q6
Q6
NC
NC
NC
X NC
L
H
L
H
X NC
NC SQ
H
SLS
SL74HC4094
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC4094
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
±5.0
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
±10
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
= 0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum Three-State
Leakage Current
V
IN
=V
CC
or GND
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
I
CC
Maximum Quiescent
Supply Current
(per Package)
6.0
4.0
40
160
µA
SLS
System Logic
Semiconductor
SL74HC4094
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
Maximum Propagation Delay, Clock to SQ
H
(Figures 1 and 5)
Maximum Propagation Delay, Clock to Q
A
-Q
H
(Figures 2 and 5)
Maximum Propagation Delay ,Output Enable to
Q
A
-Q
H
(Figures 3 and 6)
Maximu m Propagation Delay ,Output Enable to
Q
A
-Q
H
(Figures 3 and 6)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
-Q
H
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
Guaranteed Limit
25
°C
to
-55°C
6
30
35
150
30
26
195
40
33
125
25
21
175
35
30
10
15
≤85°C
5
25
28
190
38
33
245
50
42
155
31
26
220
44
37
10
15
≤125°C
4
20
23
225
45
38
295
60
50
190
38
32
265
53
45
10
15
Unit
MHz
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZL
, t
PZH
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
300
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Serial Data
Input A to Clock (Figure 4)
Minimum Hold Time, Clock to Data
Input A (Figure 4)
Minimum Pulse Width, Strobe (Figure
1)
Maximum Input Rise and Fall Times
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to
-55°C
50
10
9.0
3
3
3
80
16
14
1000
500
400
≤85°C
65
13
11
3
3
3
100
20
17
1000
500
400
≤125°C
75
15
13
3
3
3
120
24
20
1000
500
400
Unit
ns
t
h
ns
t
w
ns
t
r
, t
f
ns
SLS
System Logic
Semiconductor
SL74HC4094
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
SLS
System Logic
Semiconductor
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