HANBit
HSD32M64D8KP
Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on
Stacked 16Mx8, 4Banks, 4K Ref., 3.3V
Part No. HSD32M64D8KP
GENERAL DESCRIPTION
The HSD32M64D8KP is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists
of sixteen CMOS 16M x 8 bit(stacking chip) with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin
glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each
SDRAM. The HSD32M64D8KP is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance memory system applications All module components may be
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
•
Part Identification
HSD32M64D8KP
–
10L
HSD32M64D8KP
–
13
•
Burst mode operation
•
Auto & self refresh capability (4096 Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system clock
•
The used device is 4M x 8bit x 4Banks SDRAM
: 100MHz ( CL=3)
: 133MHz ( CL=3)
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PIN ASSIGNMENT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
Vss
NC
NC
Vcc
/WE
DQM0
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
DQM1
/CS0
NC
Vss
A0
A2
A4
A6
A8
A10
BA1
Vcc
Vcc
CLK0
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
CB2
CB3
Vss
DQ16
DQ17
PIN
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
DQ18
DQ19
Vcc
DQ20
NC
NC
/CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
CLK2
NC
WP
SDA
SCL
Vcc
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Symbol
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
Vss
NC
NC
Vcc
/CAS
DQM4
PIN
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
HSD32M64D8KP
Symbol
DQM5
/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
CLK1
NC
Vss
CKE0
/CS3
DQM6
DQM7
NC
Vcc
NC
NC
CB6
CB7
Vss
DQ48
DQ49
PIN
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
CLK3
NC
SA0
SA1
SA2
Vcc
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FUNCTIONAL BLOCK DIAGRAM
HSD32M64D8KP
Vcc
Vcc
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PIN FUNCTION DESCRIPTION
PIN
CLK
/CE
CKE
NAME
System clock
Chip enable
Clock enable
HSD32M64D8KP
INPUTT FUNCTION
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
A0 ~ A11
BA0 ~ BA1
/RAS
/CAS
Address
Bank select address
Row address strobe
Column
strobe
Address
/WE
DQM0 ~ 7
Write enable
Data
mask
input/output
DQ0 ~ 63
Vcc/Vss
Data input/output
Power supply/ground
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1.0V to 4.6V
-1.0V to 4.6V
16W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C))
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input leakage current
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SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
I
LI
MIN
3.0
2.0
-0.3
2.4
-
-10
TYP.
3.3
3.0
0
-
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
10
UNIT
V
V
V
V
V
uA
NOTE
1
2
I
OH
= -2mA
I
OL
= 2mA
3
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V
±
200 mV)
DESCRIPTION
Clock
/RAS, /CAS,/WE, CKE
CKE
/CS
DQM
Address
DQ (DQ0 ~ DQ7)
SYMBOL
C
CLK
C
IN
C
CKE
C
CS
C
DQM
C
ADD
C
OUT
MIN
10
40
10
10
5
40
64
MAX
14
60.8
15.2
15.2
7.6
60.8
96
UNITS
pF
pF
pF
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
PARAMETER
Operating current
(One bank active)
Precharge standby current
in
power-down mode
SYMBOL
CONDITION
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0mA
CKE
≤
V
IL
(max)
t
CC
=10ns
CKE & CLK
≤
V
IL
(max)
t
CC
=∞
CKE
≥
V
IH
(min)
CS*
≥
V
IH
(min), t
CC
=10ns
Input signals are changed
one time during 20ns
CKE
≥
V
IH
(min)
CLK
≤
V
IL
(max), t
CC
=∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=10ns
CKE&CLK
≤
V
IL
(max)
t
CC
=∞
CKE≥V
IH
(min),
CS*≥V
IH
(min), t
CC
=10ns
Input signals are changed
one time during 20ns
CKE≥VIH(min)
CLK
≤VIL(max),
t
CC
=∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
C
-13
1440
32
32
-10L
1440
mA
mA
mA
VERSION
UNIT
E
1
NOT
I
CC1
I
CC2
P
I
CC2
PS
Precharge standby current
in
non power-down mode
I
CC2
N
320
mA
160
80
mA
80
I
CC2
NS
Active standby current in
power-down mode
I
CC3
P
I
CC3
PS
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
480
mA
400
I
CC3
NS
Operating current
(Burst mode)
Refresh current
Self refresh current
I
CC4
I
CC5
I
CC6
1760
3200
32
1600
3040
mA
mA
mA
1
2
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