ADS1217
ADS
121
7
SBAS260B – MAY 2002 – REVISED OCTOBER 2004
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
24 BITS NO MISSING CODES
q
INL: 0.0012% of FSR (max)
q
FULL-SCALE INPUT:
±
2V
REF
q
PGA FROM 1 TO 128
q
22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
q
SINGLE CYCLE SETTLING MODE
q
PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
q
ON-CHIP 1.25V/2.5V REFERENCE
q
ON-CHIP CALIBRATION
q
SPI COMPATIBLE
q
POWER SUPPLY: 2.7V to 5.25V
q
< 1mW POWER CONSUMPTION, V
DD
= 3V
DESCRIPTION
The ADS1217 is a precision, wide dynamic range, delta-
sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-
tion operating from 2.7V to 5.25V supplies. The delta-sigma,
A/D converter provides up to 24 bits of no missing code
performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal buffering
can be selected to provide a very high input impedance for
direct connection to transducers or low-level voltage signals.
Burnout current sources are provided that allow for the
detection of an open or shorted sensor. An 8-bit Digital-to-
Analog Converter (DAC) provides an offset correction with a
range of 50% of the FSR (Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
of 128. The A/D conversion is accomplished with a 2nd-order,
delta-sigma modulator and programmable sinc filter. The
reference input is differential and can be used for ratiometric
measurements. The onboard current DACs operate indepen-
dently with the maximum current set by an external resistor.
The serial interface is SPI compatible. Eight bits of digital I/O
are also provided that can be used for input or output. The
ADS1217 is designed for high-resolution measurement appli-
cations in smart transmitters, industrial process control, weigh
scales, chromatography, and portable instrumentation.
AGND
AV
DD
R
DAC
V
REFOUT
V
RCAP
V
REF+
V
REF–
X
IN
X
OUT
APPLICATIONS
q
INDUSTRIAL PROCESS CONTROL
q
LIQUID/GAS CHROMATOGRAPHY
q
BLOOD ANALYSIS
q
SMART TRANSMITTERS
q
PORTABLE INSTRUMENTATION
q
WEIGH SCALES
q
PRESSURE TRANSDUCERS
IDAC2
8-Bit
IDAC
Clock Generator
Voltage
Reference
IDAC1
8-Bit
IDAC
Offset
DAC
PDWN
DYSNC
A
IN
0
A
IN
1
A
IN
2
A
IN
3
A
IN
4
A
IN
5
A
IN
6
A
IN
7
A
INCOM
Serial Interface
Digital I/O
Interface
POL
SCLK
D
IN
D
OUT
CS
DRDY
BUFEN
DV
DD
DGND
D0
... D7
MUX
BUF
+
PGA
2nd-Order
Modulator
Program-
mable
Digital
Filter
Controller
Registers
RAM
RESET
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002-2004, Texas Instruments Incorporated
www.ti.com
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer (mux) provides for any combination of
differential inputs to be selected on any of the input channels,
as shown in Figure 1. If channel 1 is selected as the positive
differential input channel, any other channel can be selected
as the negative differential input channel. With this method,
it is possible to have up to eight fully differential input
channels.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the pins.
BURNOUT CURRENT SOURCES
When the Burnout bit is set in the ACR configuration register,
two current sources are enabled. The current source on the
positive input channel sources approximately 2µA of current.
The current source on the negative input channel sinks ap-
proximately 2µA. This allows for the detection of an open circuit
(full-scale reading) or short circuit (0V differential reading) on
the selected input differential pair.
INPUT BUFFER
The input impedance of the ADS1217 without the buffer
is 10MΩ/PGA. With the buffer enabled, the input voltage range
is reduced and the analog power-supply current is higher. The
buffer is controlled by ANDing the state of the buffer pin with
the state of the BUFFER bit in the ACR register. See Applica-
tion Report
Input Currents for High-Resolution ADCs
(SBAA090) for more information.
A
IN
0
A
IN
1
IDAC1 AND IDAC2
AV
DD
A
IN
2
Burnout Current Source On
A
IN
3
A
IN+
A
IN
4
A
IN–
A
IN
5
The ADS1217 has two 8-bit current output DACs that can
be controlled independently. The output current is set with
R
DAC
, the range select bits in the ACR register, and the
8-bit digital value in the IDAC register. The output
current = (V
REF
/8R
DAC
) (2
RANGE–1
) (DAC CODE). With
V
REFOUT
= 2.5V and R
DAC
= 150kΩ, the full-scale output can
be selected to be 0.5, 1, or 2mA. The compliance voltage
range is AGND to within 1V of AV
DD
. When the internal
voltage reference of the ADS1217 is used, it is the refer-
ence for the IDAC. An external reference may be used for
the IDACs by disabling the internal reference and tying the
external reference input to the V
REFOUT
pin.
Burnout Current Source On
A
IN
6
AGND
IDAC1
A
IN
7
PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can improve the effective resolution of the A/D
converter. For instance, with a PGA of 1 on a 10V full-scale
range, the A/D converter can resolve to 2µV. With a PGA of
128 on a 80mV full-scale range, the A/D converter can resolve
to 150nV.
A
INCOM
FIGURE 1. Input Multiplexer Configuration.
PGA OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA by using the ODAC register. The ODAC
(Offset DAC) register is an 8-bit value; the MSB is the sign and
the seven LSBs provide the magnitude of the offset. Using the
ODAC does not reduce the performance of the A/D converter.
See Application Report
The Offset DAC
(SBAA077) for more
information.
TEMPERATURE SENSOR
An on-chip diode provides temperature sensing capability.
When the configuration register for the input MUX is set to all
1s, the diode is connected to the input of the A/D converter.
All other channels are open. The anode of the diode is
connected to the positive input of the A/D converter, and the
cathode of the diode is connected to negative input of the
A/D converter. The output of IDAC1 is connected to the
anode to bias the diode and the cathode of the diode is also
connected to ground to complete the circuit.
In this mode, the output of IDAC1 is also connected to the
output pin, so some current may flow into an external load
from IDAC1, rather than the diode. See Application Report
Measuring Temperature with the ADS1216, ADS1217, or
ADS1218
(SBAA073) for more information.
MODULATOR
The modulator is a single-loop, 2nd-order system. The modu-
lator runs at a clock speed (f
MOD
) that is derived from the
external clock (f
OSC
). The frequency division is determined by
the SPEED bit in the setup register.
SPEED BIT
0
1
f
MOD
f
OSC
/128
f
OSC
/ 256
12
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ADS1217
SBAS260B
VOLTAGE REFERENCE INPUT
The ADS1217 uses a differential voltage reference input.
The input signal is measured against the differential voltage
V
REF
≡
(V
REF+
) – (V
REF–
). For AV
DD
= 5V, V
REF
is typically
2.5V. For AV
DD
= 3V, V
REF
is typically 1.25V. Due to the
sampling nature of the modulator, the reference input current
increases with higher modulator clock frequency (f
MOD
) and
higher PGA settings.
complete both an offset and gain calibration. Self-gain cali-
bration is optimized for PGA gains less than 8. When using
higher gains, system gain calibration is recommended.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
“zero” differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive “full-scale” differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven t
DATA
periods to complete.
Calibration must be performed after power on, a change in
decimation ratio, or a change of the PGA. For operation with
a reference voltage greater than (AV
DD
– 1.5V), the buffer
must also be turned off during calibration.
At the completion of calibration, the
DRDY
signal goes LOW,
which indicates the calibration is finished and valid data is
available. See Application Report
Calibration Routine and
Register Value Generation for the ADS121x Series
(SBAA099)
for more information.
ON-CHIP VOLTAGE REFERENCE
A selectable voltage reference (1.25V or 2.5V) is available for
supplying the voltage reference input. To use, connect V
REF–
to AGND and V
REF+
to V
REFOUT
. The enabling and voltage
selection are controlled through bits REF EN and REF HI in
the setup register. The 2.5V reference requires AV
DD
= 5V.
When using the on-chip voltage reference, the V
REFOUT
pin
should be bypassed with a 0.1µF capacitor to AGND.
V
RCAP
PIN
This pin provides a bypass cap for noise filtering on internal
V
REF
circuitry only. As this is a sensitive pin, place the
capacitor as close as possible and avoid any resistive load-
ing. The recommended capacitor is a 0.001µF ceramic cap.
If an external V
REF
is used, this pin can be left unconnected.
DIGITAL FILTER
The Digital Filter can use either the fast settling, sinc
2
, or
sinc
3
filter, as shown in Figure 3. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
fast settling filter; It will then use the sinc
2
followed by the
sinc
3
filter. This combines the low-noise advantage of the
sinc
3
filter with the quick response of the fast settling time
filter. See Figure 4 for the frequency response of each filter.
When using the fast setting filter, select a decimation value
set by the DEC0 and M/DEC1 registers that is evenly
divisible by four for the best gain accuracy. For example,
choose 260 rather than 261.
Adjustable Digital Filter
CLOCK GENERATOR
The clock source for the ADS1217 can be provided from a
crystal, oscillator, or external clock. When the clock source is
a crystal, external capacitors must be provided to ensure start-
up and a stable clock frequency; see Figure 2 and Table I.
C
1
Crystal
X
IN
C
2
X
OUT
Sinc
3
Modulator
Output
C
2
PART
NUMBER
ECS, ECSD 2.45 - 32
ECS, ECSL 4.91
ECS, ECSD 4.91
CTS, MP 042 4M9182
FILTER
Sinc
3
Sinc
2
Fast
FILTER SETTLING TIME
SETTLING TIME
(Conversion Cycles)
3
2
1
FIGURE 2. Crystal Connection.
CLOCK
SOURCE
Crystal
Crystal
Crystal
Crystal
Sinc
2
Data Out
FREQUENCY
2.4576
4.9152
4.9152
4.9152
C
1
0-20pF
0-20pF
0-20pF
0-20pF
Fast Settling
0-20pF
0-20pF
0-20pF
0-20pF
TABLE I. Typical Clock Sources.
CALIBRATION
The offset and gain errors in the ADS1217, or the complete
system, can be reduced with calibration. Internal calibration
of the ADS1217 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven t
DATA
periods to complete. It takes 14 t
DATA
periods to
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
1
Fast
2
Sinc
2
3
Sinc
3
4+
Sinc
3
FIGURE 3. Filter Step Responses.
ADS1217
SBAS260B
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13
SINC
3
FILTER RESPONSE
(1)
(–3dB = 0.262 • f
DATA
= 15.76Hz)
0
–20
–40
Gain (dB)
SINC
2
FILTER RESPONSE
(1)
(–3dB = 0.318 • f
DATA
= 19.11Hz)
0
–20
–40
Gain (dB)
–60
–80
–100
–120
0
30
60
90
120
150 180
210 240 270 300
Frequency (Hz)
–60
–80
–100
–120
0
30
60
90
120
150 180
210 240 270 300
Frequency (Hz)
FAST SETTLING FILTER RESPONSE
(1)
(–3dB = 0.469 • f
DATA
= 28.125Hz)
0
–20
–40
Gain (dB)
–60
–80
–100
–120
0
30
60
90
120
150 180
210 240 270 300
Frequency (Hz)
NOTE: (1) f
DATA
= 60Hz.
FIGURE 4. Filter Frequency Responses.
DIGITAL I/O INTERFACE
The ADS1217 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as inputs.
All of the digital I/O pins are individually configurable as inputs
or outputs. They are configured through the DIR control regis-
ter. The DIR register defines whether the pin is an input or
output, and the DIO register defines the state of the digital
output. When the digital I/O are configured as inputs, DIO is
used to read the state of the pin. If the digital I/O are not used,
either 1) configure as outputs; or, 2) leave as inputs and tie to
ground, this prevents excess power dissipation.
back with no delay in SCLKs or toggling of
CS
. Make sure
to avoid glitches on SCLK as they can cause extra shifting of
the data.
Polarity (POL)
The serial clock polarity is specified by the POL input. When
SCLK is active HIGH, set POL HIGH. When SCLK is active
LOW, set POL LOW.
DATA READY
The
DRDY
output is used as a status signal to indicate when
data is ready to be read from the ADS1217.
DRDY
goes LOW
when new data is available. It is reset HIGH when a read
operation from the data register is complete. It also goes HIGH
prior to the updating of the output register to indicate when not
to read from the device to ensure that a data read is not
attempted while the register is being updated.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1217. The ADS1217
operates in slave only mode.
Chip Select (
CS
)
The chip select (CS ) input of the ADS1217 must be exter-
nally asserted before a master device can exchange data
with the ADS1217.
CS
must be LOW for the duration of the
transaction.
CS
can be tied low.
DSYNC OPERATION
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the
DSYNC
pin or the DSYNC
command. When the
DSYNC
pin is used, the filter counter is
reset on the falling edge of
DSYNC.
The modulator is held in
reset until
DSYNC
is taken HIGH. Synchronization occurs on
the next rising edge of the system clock after
DSYNC
is
taken HIGH.
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input, clocks data transfer on the D
IN
input and D
OUT
output. When transferring data to or from the
ADS1217, multiple bits of data may be transferred back-to-
14
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ADS1217
SBAS260B
When the DSYNC command is sent, the filter counter is reset
on the edge of the last SCLK on the DSYNC command. The
modulator is held in reset until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command. After a DSYNC operation,
DRDY
is held HIGH
until valid data is ready.
Configuration
Registers
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128 Bytes
Bank 0
16 bytes
RESET
There are three methods to reset the ADS1217: the
RESET
input, the RESET command, and a special SCLK input pat-
tern. When using the
RESET
input, take it LOW to force a
reset. Make sure to follow the minimum pulse width timing
specifications before taking the
RESET
input back high. Also,
avoid glitches on the
RESET
input as these may cause
accidental resets. The RESET command takes effect after all
8 bits have been shifted into DIN. Afterwards, the reset
releases automatically. The ADS1217 can also be reset with
a special pattern on SCLK, see the Timing Diagram. Reset
occurs on the falling edge of the last SCLK edge in the pattern
(for POL = 0). Afterwards, the reset releases automatically.
Bank 2
16 bytes
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotonically.
Bank 7
16 bytes
MEMORY
Two types of memory are used on the ADS1217: registers
and RAM. 16 registers directly control the various functions
(PGA, DAC value, Decimation Ratio, etc.) and can be directly
read or written. Collectively, the registers contain all the
information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio,
etc. Additional registers, such as output data, are accessed
through dedicated instructions.
FIGURE 5. Memory Organization.
The RAM provides eight “banks”, with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively with-
out having to address each bank individually. For example,
if you were currently accessing bank 0 at offset 0F
H
(the last
location of bank 0), the next access would be bank 1 and
offset 00
H
. Any access after bank 7 and offset 0F
H
will wrap
around to bank 0 and Offset 00
H
.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of
bank and offset addressing. Looking at linear and bank
addressing syntax, we have the following comparison: in the
linear memory map, the address 14
H
is equivalent to bank
1 and offset 04
H
. Simply stated, the most significant four bits
represent the bank, and the least significant four bits repre-
sent the offset. The offset is equivalent to the register
address for that bank of memory.
REGISTER BANK TOPOLOGY
The operation of the device is set up through individual
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers;
that is, the RAM can be used as general-purpose RAM.
The ADS1217 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations—one per input channel. In order
to facilitate this type of usage, eight separate register banks
are available. Therefore, each configuration could be written
once and recalled as needed without having to serially
retransmit all the configuration data. Checksum commands
are also included, which can be used to verify the integrity of
RAM.
ADS1217
SBAS260B
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15
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