HANBit
Synchronous
DRAM
Module
256Mbyte
HSD32M64B8A
(32Mx64Bit),
SO-DIMM,
4Banks, 8K Ref., 3.3V
Part No. HSD32M64B8A
GENERAL DESCRIPTION
The HSD32M64B8A is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists
of eight CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The
HSD32M64B8A is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance memory system applications All module components may be
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
•
Part Identification
HSD32M64B8A-F/10L : 100MHz (CL=3)
HSD32M64B8A-F/10 : 100MHz (CL=2)
HSD32M64B8A-F/12 : 125MHz (CL=3)
HSD32M64B8A-F/13 : 133MHz (CL=3)
F means Auto & Self refresh with Low-Power (3.3V)
•
Burst mode operation
•
Auto & self refresh capability (8192 Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system clock
•
The used device is 8M x 8bit x 4Banks Synchronous DRAM
URL:www.hbe.co.kr
REV.1.0(August.2002)
1
HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
Vss
DQM0
DQM1
VDD
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Symbol
Vss
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
VDD
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
PIN
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
Symbol
DQ13
DQ14
DQ15
Vss
NC
NC
CLK0
VDD
/RAS
/WE
/CS0
NC
NC
Vss
NC
NC
VDD
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
PIN
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Symbol
DQ45
DQ46
DQ47
Vss
NC
NC
CKE0
VDD
/CAS
NC
A12
NC
CLK1
Vss
NC
NC
VDD
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
PIN
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
HSD32M64B8A
Symbol
DQ22
DQ23
VDD
A6
A8
Vss
A9
A10_AP
VDD
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
Vss
**SDA
VDD
PIN
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Symbol
DQ54
DQ55
VDD
A7
BA0
Vss
BA1
A11
VDD
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
Vss
**SCL
VDD
** These pins should be NC in the system which does not support SPD
URL:www.hbe.co.kr
REV.1.0(August.2002)
2
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
HSD32M64B8A
CKE0
/CAS
/RAS
/CS0
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
WE
WE
WE
U1
A0-A12
CLK
DQ8-15
DQM1
BA0-1
CLK
DQ8-15
DQM1
CLKA
DQM0
U2
DQM1
A0-A12
BA0-1
CLK
DQ16-23
DQM2
U3
CLKB
DQM2
A0-A12
BA0-1
CKE
CAS
RAS
CE
WE
U4
CLK
DQ24-31
DQM3
DQM3
A0-A12
BA0-1
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
CKE
CAS
RAS
CE
WE
WE
WE
U5
CLK
DQ32-39
DQM4
CLKC
DQM4
A0-A12
BA0-1
CLK
DQ40-47
DQM5
U6
DQM5
A0-A12
BA0-1
CLK
DQ48-55
DQM6
U7
CLKD
DQM6
A0-A12
BA0-1
CKE
CAS
RAS
CE
WE
U8
CLK
DQ56-63
DQM7
DQM7
A0-A12
BA0-1
/WE
A0 - A12
BA0-1
CLKA
Vcc
Vss
URL:www.hbe.co.kr
REV.1.0(August.2002)
Two 0.1uF Capacitors
per each SDRAM
CLKB
CLKC
CLKD
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HANBit
PIN FUNCTION DESCRIPTION
Pin
CLK
/CS
Name
System clock
Chip enable
Input Function
HSD32M64B8A
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column
strobe
address
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~ 7
Data
mask
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
DQ0 ~ 63
Vcc/Vss
Data input/output
Power
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 4.6V
-1V to 4.6V
8W
-55oC to 150oC
Short Circuit Output Current
I
OS
400mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr
REV.1.0(August.2002)
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HANBit Electronics Co.,Ltd.
HANBit
HSD32M64B8A
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
MIN
3.0
2.0
-0.3
2.4
-
TYP.
3.3
3.0
0
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
UNIT
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
NOTE
Input leakage current
I
LI
-10
-
10
uA
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V
±
200 mV)
DESCRIPTION
Clock
Address
/RAS, /CAS, /WE, /CS, CKE, DQM
DQ (DQ0 ~ DQ15)
SYMBOL
C
CLK
C
ADD
C
IN
C
OUT
MIN
2.5
2.5
2.5
4.0
MAX
4.0
5.0
5.0
6.5
UNITS
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)
TEST
PARAMETER
SYMBOL
CONDITION
Burst length = 1
Operating current
(One bank active)
I
CC1
t
RC
≥
t
RC
(min)
I
O
= 0mA
I
CC2
P
CKE
≤
V
IL
(max)
t
CC
=10ns
CKE & CLK
≤
V
IL
(max)
t
CC
=∞
CKE
≥
V
IH
(min)
Precharge standby current in
non power-down mode
I
CC2
N
CS*
≥
V
IH
(min),
t
CC
=10ns
128
mA
16
mA
16
mA
960
960
880
880
mA
1
-13
-12
-10
-10L
VERSION
UNIT
NOTE
Precharge standby current in
power-down mode
I
CC2
PS
Input signals are changed
one time during 20ns
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REV.1.0(August.2002)
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