HSD16M32M4V-10 datasheet, PDF - EEWORLD Datasheet

HANBit

HSD16M32M4V

Synchronous DRAM Module 64Mbyte ( 16M x 32-Bit ) 72-Pin SIMM based on

16Mx8, 4Banks, 4K Ref., 3.3V

Part No.

HSD16M32M4V

GENERAL DESCRIPTION

The HSD16M32M4V is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists

of four CMOS 4M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages mounted on a 72-pin, FR-4-printed

circuit board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The

HSD16M32M4V is a SIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O

transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same

device to be useful for a variety of high bandwidth, high performance memory system applications All module

components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

•

Part Identification

HSD16M32M4V-13/F13 :133MHz ( CL=3)

HSD16M32M4V-12/F12: 125MHz (CL=3)

HSD16M32M4V-10/F10: 100MHz (CL=2)

HSD16M32M4V-10L/F10L: 100MHz

HSD16M32M4V-66/F66: 66MHz (CL=2&3)

F means Auto & Self refresh with Low-Power (3.3V)

•

Burst mode operation

•

Auto & self refresh capability (4096 Cycles/64ms)

•

LVTTL compatible inputs and outputs

•

Single 3.3V

±0.3V

power supply

•

MRS cycle with address key programs

- Latency (Access from column address)

- Burst length (1, 2, 4, 8 & Full page)

- Data scramble (Sequential & Interleave)

•

All inputs are sampled at the positive going edge

of the system clock

•

FR4-PCB design

•

The used device is KM48S16030AT

•

Pin assignment is compatible with

- HSD8M32M4V

- HSD32M32M4V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

PIN ASSIGNMENT

SYMBOL

Vss

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM0

Vcc

NC

A0

A1

A2

A3

A4

Vss

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SYMBOL

DQ14

DQ15

DQM1

NC

/WE

/CAS

Vcc

/RAS

/CS0

NC

CLK0

CKE0

Vss

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM2

Vcc

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

SYMBOL

A5

A6

A7

A8

A9

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQM3

NC

A10/AP

A11

NC

Vcc

BA0

BA1

NC

Vss

72-PIN SIMM TOP VIEW

URL:

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REV 1.0 (August.2002)

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FUNCTIONAL BLOCK DIAGRAM

DQ0-31

HSD16M32M4V

CKE0

/CA

S

/RAS

/CE1

CKE

CAS

RAS

CE

1

WE

A0-A11

CLK

CLK0

U1

DQ0-7

DQM0

BA0-

DQM0

CKE

CAS

15

RAS

CE

1

WE

A0-A11

CLK

CLK0

U2

DQ8-

DQM1

DQM0

BA0-

CKE

CAS

23

RAS

CE

1

WE

A0-A11

CLK

CLK0

U3

DQ16-

DQM2

DQM0

BA0-

CKE

CAS

31

RAS

CE

1

WE

A0-A11

CLK

CLK0

U4

DQ24-

DQM3

DQM0

BA0-

/WE

A0 - A11

BA0-1

Vcc

Vss

Two 0.01uF Capacitor

per each SDRAM

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REV 1.0 (August.2002)

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PIN FUNCTION DESCRIPTION

CLK

/CE

Name

System clock

Chip enable

Input Function

HSD16M32M4V

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+tSS prior to valid command.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

BA0

BA1

/RAS

~

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

/CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

/WE

Write enable

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM0 ~ 3

Data input/output mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

DQ0 ~ 31

VDD/VSS

Data input/output

Power supply/ground

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Voltage on Any Pin Relative to Vss

Voltage on Vcc Supply Relative to Vss

Power Dissipation

Storage Temperature

SYMBOL

V

IN ,OUT

Vcc

P

D

T

STG

RATING

-1V to 4.6V

4W

-55oC to 150oC

Short Circuit Output Current

I

OS

50mA

Notes :

Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be

restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

URL:

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REV 1.0 (August.2002)

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HSD16M32M4V

DC OPERATING CONDITIONS

(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) )

PARAMETER

Supply Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

SYMBOL

Vcc

V

IH

V

IL

V

OH

V

OL

MIN

3.0

2.0

-0.3

2.4

-

TYP.

3.3

3.0

0

-

MAX

3.6

Vcc+0.3

0.8

-

0.4

UNIT

V

1

2

I

OH

= -2mA

I

OL

= 2mA

3

NOTE

Input leakage current

I

LI

-10

-

10

uA

Notes :

1. V

IH

(max) = 5.6V AC. The overshoot voltage duration is

≤

3ns.

2. V

IL

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

V

IN

≤

V

DDQ

.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

(VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V

±

200 mV)

DESCRIPTION

Address(A0~A12, BA0~BA1)

/RAS, /CAS, /WE

CKE(CKE0)

Clock (CLK0)

/CE (/CE1)

DQM (DQM0 ~ DQM3)

DQ (DQ0 ~ DQ32)

SYMBOL

C

ADD

C

IN

C

CKE

C

CLK

C

CS

C

DQM

C

OUT

MIN

15

7.5

15

6.5

7

MAX

25

9

25

7.5

8.5

UNITS

pF

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)

TEST

PARAMETER

SYMBOL

CONDITION

Burst length = 1

Operating current

I

CC1

(One bank active)

t

RC

≥

t

RC

(min)

I

O

= 0mA

Precharge standby current

in

power-down mode

I

CC2

PS

I

CC2

P

CKE

≤

V

IL

(max)

t

CC

=10ns

CKE & CLK

≤

V

IL

(max)

t

CC

=∞

4

mA

4

mA

48

440

0

440

0

44

440

mA

1

-A

-8

-H

-L

-10

VERSION

UNIT

E

NOT

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REV 1.0 (August.2002)

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CKE

≥

V

IH

(min)

I

CC2

N

Precharge standby current

in

non power-down mode

I

CC2

NS

CS*

≥

V

IH

(min), t

CC

=10ns

Input signals are changed

one time during 20ns

CKE

≥

V

IH

(min)

CLK

≤

V

IL

(max), t

CC

=∞

Input signals are stable

I

CC3

P

Active standby current in

power-down mode

I

CC3

PS

CKE

≤

V

IL

(max), t

CC

=10ns

CKE&CLK

≤

V

IL

(max)

t

CC

=∞

CKE≥V

IH

(min),

CS*≥V

IH

(min), t

CC

=10ns

I

CC3

N

Active standby current in

non power-down mode

(One bank active)

I

CC3

NS

Input signals are changed

one time during 20ns

CKE≥VIH(min)

CLK

≤VIL(max),

t

CC

=∞

Input signals are stable

I

O

= 0 mA

Operating current

I

CC4

(Burst mode)

4Banks Activated

t

CCD

= 2CLKs

Refresh current

I

CC5

t

RC

≥

t

RC

(min)

88

880

0

6

3.2

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

).

840

0

Page burst

60

580

500

80

120

20

28

80

HSD16M32M4V

mA

20

mA

500

mA

1

840

mA

2

G

F

Self refresh current

I

CC6

CKE

≤

0.2V

AC OPERATING TEST CONDITIONS

(vcc = 3.3V

±

0.3V, TA = 0 to 70° C)

PARAMETER

AC Input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

UNIT

V

ns

V

URL:

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REV 1.0 (August.2002)

-5-

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Parameter Name	Attribute value
Maker	HANBIT Electronics
package instruction	,
Reach Compliance Code	unknown

	HSD16M32M4V-10	HSD16M32M4V-12	HSD16M32M4V-F10	HSD16M32M4V-F12	HSD16M32M4V	HSD16M32M4V-10L	HSD16M32M4V-13
Description	synchronous dram module 64mbyte ( ref='/w_16m.html'>16m x 32-ref='/w_bit.html'>bit ) 72-ref='/w_pin.html'>pin simm based on ref='/w_16m.html'>16mx8, 4banks, 4K ref., 3.3V	synchronous dram module 64mbyte ( ref='/w_16m.html'>16m x 32-ref='/w_bit.html'>bit ) 72-ref='/w_pin.html'>pin simm based on ref='/w_16m.html'>16mx8, 4banks, 4K ref., 3.3V	synchronous dram module 64mbyte ( ref='/w_16m.html'>16m x 32-ref='/w_bit.html'>bit ) 72-ref='/w_pin.html'>pin simm based on ref='/w_16m.html'>16mx8, 4banks, 4K ref., 3.3V	synchronous dram module 64mbyte ( ref='/w_16m.html'>16m x 32-ref='/w_bit.html'>bit ) 72-ref='/w_pin.html'>pin simm based on ref='/w_16m.html'>16mx8, 4banks, 4K ref., 3.3V	synchronous dram module 64mbyte ( ref='/w_16m.html'>16m x 32-ref='/w_bit.html'>bit ) 72-ref='/w_pin.html'>pin simm based on ref='/w_16m.html'>16mx8, 4banks, 4K ref., 3.3V	synchronous dram module 64mbyte ( ref='/w_16m.html'>16m x 32-ref='/w_bit.html'>bit ) 72-ref='/w_pin.html'>pin simm based on ref='/w_16m.html'>16mx8, 4banks, 4K ref., 3.3V	synchronous dram module 64mbyte ( ref='/w_16m.html'>16m x 32-ref='/w_bit.html'>bit ) 72-ref='/w_pin.html'>pin simm based on ref='/w_16m.html'>16mx8, 4banks, 4K ref., 3.3V
Maker	HANBIT Electronics	HANBIT Electronics	HANBIT Electronics	HANBIT Electronics	-	HANBIT Electronics	HANBIT Electronics
Reach Compliance Code	unknown	unknown	unknown	unknown	-	unknown	unknown

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