NOTES: (1) 100% tested at rated continuous for one minute. (2) Isolation-mode rejection is the ratio of the change in output voltage to a change in isolation barrier voltage.
It is a function of frequency as shown in the Typical Performance Curves. This is specified for barrier voltage slew rates not exceeding 100V/µs. (3) Adjustable to zero.
FSR = Full Scale Range = 20V. (4) Nonlinearity is the peak deviation of the output voltage from the best fit straight line. It is expressed as the ratio of deviation to FSR.
(5) Power supply rejection = change in V
OS
/20V supply change. (6) Ripple is the residual component of the barrier carrier frequency generated internally. (7) Dynamic
range = FSR/(voltage spectral noise density
x
square root of user bandwidth). (8) Overshoot can be eliminated by band-limiting. (9) See “Power Dissipation vs
Temperature” performance curve for limitations. (10) Band limited to 10Hz, bypass capacitors located less than 0.25" from supply pins.
ORDERING INFORMATION
MODEL
ISO102
ISO102B
ISO106
ISO106B
PACKAGE
Ceramic
Ceramic
Ceramic
Ceramic
TEMPERATURE
RANGE
–25°C
–25°C
–25°C
–25°C
to
to
to
to
+85°C
+85°C
+85°C
+85°C
ABSOLUTE MAXIMUM RATINGS
Supply Without Damage ....................................................................
±20V
Input Voltage Range ..........................................................................
Junction Temperature .................................................................... +160°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Amplifier and Reference Output
Short Circuit Duration ....................................... Continuous to Common
PACKAGE INFORMATION
(1)
MODEL
ISO102
ISO102B
ISO106
ISO106B
PACKAGE
24-Pin Ceramic
24-Pin Ceramic
40-Pin Ceramic
40-Pin Ceramic
PACKAGE DRAWING
NUMBER
208
208
206
206
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
ISO102/106
PIN CONFIGURATION
ISO102
–V
CC1
V
IN
Gain Adjust
Common
1
Isolation
Barrier
C
1
Common
2
Reference
2
+V
CC2
9
10
11
12
16
15
14
13
Digital Common
C
2
V
OUT
–V
CC2
1
2
3
4
24
23
22
21
+V
CC1
Offset Adjust
Offset
Reference
1
Isolation
Barrier
C
1
Common
2
Reference
2
+V
CC2
17
18
19
20
24
23
22
21
Digital Common
C
2
V
OUT
–V
CC2
–V
CC1
V
IN
Gain Adjust
Common
1
1
2
3
4
ISO106
40
39
38
37
+V
CC1
Offset Adjust
Offset
Reference
1
PIN DESCRIPTIONS
±V
CC1
,
Common
1
±V
CC2
,
Common
2
V
IN
Gain
Adjust
Reference
1
Positive and negative power supply voltages and common (or ground) for the input stage. Common
1
is the analog reference voltage for input
signals. The voltage between Common
1
and Common
2
is the isolation voltage and appears across the internal high voltage barrier.
Positive and negative power supply voltages and common (or ground) for the output stage. Common
2
is the analog reference voltage for output
signals. The voltage between Common
1
and Common
2
is the isolation voltage and appears across the internal high voltage barrier.
Signal input pin. Input impedance is typically 100kΩ. The input range is rated for
±10V.
The input level can actually exceed the input stage
supplies. Output signal swing is limited only by the output supply voltages.
This pin is an optional signal input. A series 5kΩ potentiometer between this pin and the input signal allows a guaranteed
±1.5%
gain adjustment
range. When gain adjustment is not required, the Gain Adjust should be left open. Figure 4 illustrates the gain adjustment connection.
+5V reference output. This low-drift zener voltage reference is necessary for setting the bipolar offset point of the input stage.
This pin must
be strapped to either Offset or Offset Adjust to allow the isolation amplifier to function.
The reference is often useful for input signal
conditioning circuits. See “Effect of Reference Loading on Offset” performance curve for the effect of offset voltage change with reference loading.
Reference
1
is identical to, but independent of, Reference
2
. This output is short circuit protected.
+5V reference output. This reference circuit is identical to, but independent of, Reference
1
. It controls the bipolar offset of the output stage through
an internal connection. This output is short-circuit protected.
Offset input.
This input must be strapped to Reference
1
unless user adjustment of bipolar offset is required.
This pin is for optional offset control. When connected to the Reference
1
pin through a 1kΩ potentiometer,
±150mV
of adjustment range is
guaranteed. Under this condition, the Offset pin should be connected to the Offset Adjust pin. When offset adjustment is not required, the Offset
Adjust pin is left open. See Figure 4.
Digital common or ground. This separate ground carries currents from the digital portions of the output stage circuit. The best grounding practi-
ces require that digital common current does not flow in analog common connections. Both pins can be tied directly to a ground plane if available.
Difference in potentials between the Common
2
and Digital Common pins can be
±1V.
See Figure 2.
Signal output. Because the isolation amplifier has unity gain, the output signal is ideally identical to the input signal. The output is low impedance
and is short-circuit protected. This signal is referenced to Common
2
; subsequent circuitry should have a separate “sense” connection to Common
1
as well as V
OUT
.
Capacitors for small signal bandwidth control. These pins connect to the internal rolloff frequency controlling nodes of the output low-pass filter.
Additional capacitance added to these pins will modify the bandwidth of the buffer. C
2
is always twice the value of C
1
. See “Bandwidth Control”
performance curve for the relationship between bandwidth and C
1
and C
2
. When no connections are made to these pins, the full small-signal
bandwidth is maintained. Be sure to shield C
1
and C
2
pins from high electric fields on the PC board. This preserves AC isolation-mode rejection
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51mcu
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