P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C1981/1981L
– 5.5 mW Standby (CMOS Input)
P4C1981L/82L (Military)
Output Enable and Dual Chip Enable Functions
P4C1981/1981L, P4C1982/1982L
5V
±
10% Power Supply
Data Retention with 2.0V Supply, 10
µ
A Typical
Current (P4C1981L/1982L (Military)
Separate Inputs and Outputs
– P4C1981/L Input Data at Outputs during Write
– P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
DESCRIPTION
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when
OE
is low; the outputs of
the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V
±
10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is typically
10
µA
from 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby. For the P4C1982L and
P4C1981L, power is only 5.5 mW standby with CMOS
input levels. The P4C1981/L and P4C1982/L are mem-
bers of a family of PACE RAM™ products offering fast
access times.
The P4C1981/L and P4C1982/L are available in 28-pin
300 mil DIP and SOJ, and in 28-pin 350x550 mil LCC
packages providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
A
(8)
A
I
1
I
2
I
3
I
4
O
1
O
2
O
3
O
4
ROW
SELECT
65,536-BIT
MEMORY
ARRAY
PIN CONFIGURATIONS
VCC
A 13
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I
1
COLUMN
SELECT
INPUT
DATA
CONTROL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A13
A 12
A11
A10
A9
I4
I3
A3
A4
A5
A6
A7
A8
I1
I2
CE
1
3
4
5
6
7
8
9
10
11
12
13
OE
A2
A1
A0
2
1
28
27
26
25
24
23
22
21
20
19
A12
A11
A10
A9
I4
I3
O4
O3
O2
COLUMN I/O
O4
O3
O2
O1
WE
CE
2
I
2
CE
1
OE
GND
14 15 16
GND
CE
2
18
17
CE
2
WE
OE
P4C1982
P4C1981
A
(6)
A
DIP (P5, D5-2), SOJ (J5)
TOP VIEW
P4C1981/ 1982
LCC (L5)
TOP VIEW
Means Quality, Service and Speed
1Q97
81
WE
O1
CE
1
P4C1981/1981L, P4C1982/1982L
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
V
°C
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
5.0V
±
10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
–55°C to +125°C
–40°C to +85°C
Industrial
0°C to +70°C
Commercial
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= –18 mA
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
1
,
CE
2
= V
IH
V
OUT
= GND to V
CC
Mil.
Com’l.
Mil.
Ind./Com’l.
2.4
–10
–5
–10
–5
___
___
___
___
+10
+5
+10
+5
40
35
20
15
Test Conditions
P4C1981 / 1982
Min
Max
2.2
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–5
n/a
–5
n/a
___
___
___
___
+5
n/a
+5
n/a
40
n/a
1.0
n/a
P4C1981L / 82L
Unit
Min
Max
V
CC
+0.5
2.2
V
CC
+0.5 V
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
V
V
V
V
V
V
µA
µA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
I
SB
Standby Power Supply
CE
1
,
CE
2
≥
V
IH
,
Mil.
Current (TTL Input Levels) V
CC
= Max.,
Ind./Com’l.
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
1
,
CE
2
≥
V
HC,
Mil.
V
CC
= Max.,
Ind./Com’l.
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
mA
I
SB1
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM ratingconditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
82
P4C1981/1981L, P4C1982/1982L
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Data Valid
2
2
2
10
-10
12
10
10
2
2
6
6
2
6
0
10
0
-12
-15
15
12
12
2
2
7
7
2
7
0
12
15
9
0
8
8
2
15
15
2
2
20
-20
25
20
20
2
2
10
12
2
9
0
20
-25
35
25
25
2
2
10
15
2
10
0
25
-35
45
35
35
2
2
15
21
2
14
0
25
-45
Unit
ns
Min Max Min
Max Min Max Min Max Min Max Min Max Min Max
45
45
ns
ns
ns
ns
15
27
ns
ns
ns
15
ns
ns
30
ns
t
OLZ
Output Enable to
Output in Low Z
t
OHZ
Output Disable to
Output in High Z
t
PU
t
PD
Chip Enable to
Power Up Time
Chip Disable to
Power Down Time
OE
READ CYCLE NO.1 (OE controlled)
(5)
t
RC
ADDRESS
t
AA
OE
t
OE
CE
1,
CE
2
t
LZ
(9)
DATA OUT
t
OLZ
(9)
t
AC
t
OHZ
(9)
t
HZ
(9)
t
OH
(10)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
,
CE
2
and
OE
are LOW for READ Cycle.
7.
OE
is LOW for the cycle.
8. ADDRESS must be valid prior to or coincident with,
CE
1
, and
CE
2
transition LOW.
9. Transition is measured
±200mV
from steady state voltage
prior to change, with loading as specified in Figure 1.
10. Read Cycle Time is measured from the last valid address to
the first transitioning address.
84
FPGA/CPLD
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