MT90210
Multi-Rate Parallel Access Circuit
Preliminary Information
Features
•
Parallel-to-serial and serial-to-parallel
conversion of up to 1536 full duplex channels or
3072 time-slots
Serial port data rates selectable between 2.048,
4.096 or 8.192 Mb/s
Provides a mechanism for a double buffer
function to be implemented in external memory
24 serial I/O lines programmable in different
modes: 12 in/12 out at 8.192 Mb/s (1536 full
duplex channels) or 24 bidirectional line modes
for 2.048 and 4.096 Mb/s
Provides a bidirectional 8-bit parallel port
operating at 16.384 or 32.768 MByte/s for direct
interface to external memory (dual port)
Provides an external 13-bit output address bus
for direct connection with an 8K-position dual
port memory
JTAG boundary scan
DS5026
ISSUE 2
August 1998
Ordering Information
MT90210AL
100 Pin PQFP
•
•
•
-40 to +85°C
Description
The MT90210 is a 100-pin device used to interface a
parallel bidirectional 8 bit bus to 24 time division
multiplexed (TDM) serial streams. The device is
configured to perform simultaneous parallel-to-serial
and serial-to-parallel conversion with the capability
of handling up to 3072 channels, 1536 on the
transmit and 1536 on the receive direction.
Depending on the operation mode selected at the
mode pins, the individual 64 Kb/s channels on the
serial links may be configured as inputs or outputs.
The data on the parallel bus is in a format suitable for
interfacing with a dual-port RAM. Depending on the
data rate selected by the MD0-MD2 input pins, serial
data is clocked in and out on the serial streams at
either 2.048, 4.096 or 8.192 Mb/s.
•
•
•
Applications
•
•
•
•
Fast access to ST-BUS, SCSA, MVIP, and
H-MVIP serial backplanes
Voice processing cards for Computer Telephony
Integration (CTI)
Video and teleconferencing bridge cards
Fast DSP access to serial TDM buses
RDin Strobe RBC R/W1 R/W2
S0
External Memory
Access Control
Shift
Registers
Timing
Generation
Address Generator
Read
Write
Counter
Counter
Boundary
Scan Test
MUX
Mode Control
Analog
PLL
P0
•
•
P7
WBC
SCLK
HC4
C16-
C16+
F0i
PCLK
PLLVSS
LP1,LP2
PLLAGND
CKout
RST
PLLVDD
•
•
•
•
•
•
•
•
S23
TDI
TCK
TMS
TRST
TDO
Figure 1 - Functional Block Diagram
2-145
A12
A0
OEser MD2 MD1 MD0
•
•
•
•
•
•
•
•
MT90210
Preliminary Information
A6
A7
VSS
A8
A9
VDD
A10
VSS
A11
A12
RBC
VDD
VSS
WBC
S0
S1
S2
VSS
VDD
S3
80
82
A5
VSS
VDD
A4
A3
A2
VSS
A1
A0
VDD
Strobe
VSS
P7
P6
P5
VSS
P4
VDD
P3
P2
VSS
P1
P0
R/W2
R/W1
VDD2
CKout
PCLK
RST
PLLVDD
78
76
74
72
70
68
66
64
62
60
58
56
54
52 50
48
84
46
86
44
88
42
90
92
94
36
96
34
98
32
100
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
40
38
100 PIN PQFP
PLLAGND
LP1
LP2
PLLVSS
IDDTN
TD
VSS2
C16-
C16+
VDD2
MD0
MD1
MD2
F0i
TRST
TCK
TMS
TDI
HC4
SCLK
Note: the PQFP package meets the JEDEC standard MO-108, CC1.
Critical dimensions:
Lead pitch = 0.65mm,
Body Size = 14mm x 20mm,
Package size = 17.9mm x 23.9mm.
Pin Description
Pin
95-97,
100,
1-3,
6
7-9,
11-15
18-22,
24-26
27
29
30
Name
S0-S2,
S3,
S4-S6,
S7
S8-S10,
S11-S15
S16-S20
S21-S23
TDO
RDin
OEser
Description
Serial Lines 0-7
(TTL compatible with internal pullups in the range 25 - 125kΩ).
Bidirectional, time division multiplexed serial streams. According to mode selected by
MD0-2 inputs, distinct data rates can be selected at the serial port. In mode 3, these lines
are configured as inputs only. In modes 1, 2, 4 and 5, these lines become bidirectional.
Serial Lines 8-15.
See description for S0-S7 above. In mode 3, S8-S11 are inputs and
S12-S15 are outputs. In modes 1, 2, 4 and 5 these are bidirectional lines.
Serial Lines 16-23.
See descripton for S0 - S7 above. For mode 3, these lines are outputs
and operate at 8.192 Mb/s rates. When operating in modes 1, 2, 4 and 5, these lines are
bidirectional.
Boundary Scan Test Data Output.
Read P0-P7 input clock.
This input is used by the MT90210 to sample bytes coming in at
the parallel port P0-P7 lines. Typically, the user should connect CKout to this input.
Serial Port Output Enable (Input).
On the parallel-to serial conversion direction, this input
is used by the MT90210 to know which time-slots on the serial output streams will be
placed in high-impedance. This input is sampled synchronously along with the parallel
input data before the parallel-to-serial conversion takes place. When low, output serial
channels are actively driven. When set high, the output bus drivers are disabled.
2-146
S4
S5
S6
VDD
VSS
S7
S8
S9
S10
VSS
S11
S12
S13
S14
S15
VDD
VSS
S16
S17
S18
S19
S20
VSS
S21
S22
S23
TDO
VSS2
RDin
OEser
Figure 2 - Pin Connections
Preliminary Information
Pin Description (continued)
Pin
31
Name
SCLK
Description
MT90210
Serial Port Clock (input).
The SCLK clock is used to control the serial port operation in
modes 1,2,3 and 4. Depending on the operation mode selected at the MD0-MD2 inputs,
this input can accept 4.096 (MD2-0=000), 8.192 (MD2-0=001) or 16.384 (MD2-0 =010 and
011) MHz clock. In mode 5, this input is ignored.
H-MVIP C4.
This is a 4.096 MHz clock utilized in modes 4 and 5 to maintain compatibility
with existing MVIP-90 systems. It is utilized to sample the frame pulse input (F0i). Not used
in Modes 1 - 3.
Boundary Scan Test Data Input.
Boundary Scan Test Mode Select.
Boundary Scan Test Clock.
Boundary Scan Test Reset.
Frame Synchronization Signal (TTL compatible input).
This input signal establishes
the frame boundary for the serial input/output streams.
32
HC4
33
34
35
36
37
38-40
TDI
TMS
TCK
TRST
F0i
MD2-MD0
Operation Mode Bits 0-2 (Input).
Selects the data rate for the time division, multiplexed
serial streams. 2.048 (mode 1, MD2-0=000), 4.096 (mode 2, MD2-0=001) or 8.192 (mode
3, MD2-0=010) Mb/s data rates are available. When MD2-0 are set to 011 (mode 4), the
MT90210 operates in mixed data rates mode where S16-23 operate at 8.192 Mb/s and the
remaining serial streams run at 2.048 Mb/s. In mode 5 (MD2-0=100), the MT90210
operates as per mode 4 but the device will accept a differential clock reference at 16.384
MHz at pins C16+ and C16-.
C16+
C16-
TD
IDDTN
PLLVSS
LP2
LP1
Serial Port Clock Input.
In mode 5 (MD2-0= 100), this is a 16.384 MHz differential signal.
Note used in Modes 1 - 3.
Serial Port Clock Input.
The complement to C16+.
Reserved
- Do not connect.
Connect to Ground.
PLL Ground Input.
Loop Filter Input.
An external RC circuit is required at this input, refer to Figure 10.
Loop Filter Input.
An external RC circuit is required at this input, refer to Figure 10.
42
43
45
46
47
48
49
50
51
52
53
54
PLLAGND
PLL Analog Ground output.
Provides ground to PLL loop filter, refer to Figure 10.
PLLVDD
RST
PCLK
CKout
PLL Power Input.
+5V
RESET.
A low on this pin resets the device.
Parallel Port Clock Input.
CKout must be connected to this input.
Internal VCO Output Signal.
Output of internal PLL frequency multiplier. In mode 1 the
frequency is 16.384 MHz, for the other modes the frequency is 32.768 MHz. Must be
connected to PCLK only.
Read/Write Output 1.
This output signal toggles low for the last half of a memory write
cycle indicating valid data.
Read/Write Output 2.
This output is low for memory read operations and high for memory
write operations.
56
57
R/W1
R/W2
2-147
MT90210
Pin Description (continued)
Pin
58-59,
61-62,
64,
66-68
70
Name
P0-P1,
P2-P3,
P4,
P5-P7
Strobe
Description
Preliminary Information
Parallel Input/Output Data Bus.
This 8 bit data bus is a bidirectional parallel port used to
perform 8-bit transactions between the MT90210 and the external dual port RAM. Data is
clocked in and out of the P0-P7 parallel port according to Figures 22 and 23.
Strobe Output.
This output is typically connected to the Chip-enable input of the external
dual port RAM. It is kept low during all read cycles, stays high during inactive periods and
goes low for the last half of a memory write cycle.
External Memory Address Outputs A0-A12.
These 13 address output lines are provided
by the MT90210 to allow a direct connection to an external dual port RAM.
72-73,
75- 77,
80-82,
84-85,
87,
89-90
91
A0-A1,
A2-A4,
A5-A7,
A8-A9,
A10,
A11-A12
RBC
Read Data Block Complete (output).
A transition on this output is used to notify the
external CPU that the MT90210 has finished reading the contents of one entire 125µs
frame from the external dual port memory (e.g.; from addresses 0000h to 0FFFh in modes
3, 4 or 5). Whenever RBC toggles, the MT90210 starts reading the next half of the memory
(addresses 1000h to 1FFFh) while the local CPU updates the first half with more data to
be sent. RBC toggles every 125µs. When this signal is low, the MT90210 is reading the
lower memory block.
Write Data Block Complete (Output).
A transition on this output is used to notify the
external CPU that the MT90210 has finished writing the contents of one entire 125µs
frame into the external dual port memory (e.g; from addresses 0000h to 0FFFh in modes
3,4 or 5). Once WBC toggles, the local CPU can access the Dual port memory to get the
data while the MT90210 writes the contents of the next 125µs frame into the other half
(addresses 1000h to 1FFFh) of the dual port memory. WBC toggles every 125µs. When
this signal is low, the MT90210 is writing to the lower memory block.
Supply Input.
+5V.
94
WBC
4,16,
63, 71,
78, 86,
92, 99
41, 55
5,10,
17, 23,
60, 65,
69, 74,
79,83,
88, 93,
98
28
V
DD
V
DD2
V
SS
Supply Input.
+5V.
Ground.
V
SS2
Ground.
2-148
Preliminary Information
Functional Description
The MT90210 is a 100-pin device that converts
incoming serial telecom streams of 2.048, 4.096 or
8.192 Mb/s on to an 8-bit parallel bus, and converts
input data on this parallel bus to the outgoing serial
telecom links. The device is configured to perform
simultaneous parallel-to-serial and serial-to-parallel
conversion.
MT90210 interfaces up to 24 bidirectional serial data
streams to a byte oriented parallel port for access by
a dual-port RAM. It contains an address generator
for parallel port read and write operations directly to
an external dual port memory. A single MT90210
device can handle up to 3072 channels, 1536 on the
transmit and 1536 on the receive direction.
Depending on the operation mode selected at the
mode pins (MD0-MD2), the 64 kb/s serial telecom
channels may be configured as inputs or outputs.
The data on the parallel bus is in a format suitable for
interfacing with popular dual port memories.
Depending on the data rate selected by the MD0-
MD2 input pins, serial data is clocked in and out on
the serial streams at either 2.048, 4.096 or 8.192
Mb/s, as shown in Figure 6. A mechanism for
implementing external double buffering is provided
by the Write Block Complete (WBC) and Read Block
Complete (RBC) output pins. Double buffering the
data allows the processor to independently access
an entire frame of data in the external memory while
the MT90210 reads or writes the complementary
frame in the memory. For example, in mode 3 (Figure
4), during the first frame the MT90210 will read and
write in to the first half of the memory space (Block
0) and during the second frame the MT90210 will
read and write in to the second half of the memory
space (Block 1). Within each block the transmit data
and receive data are separated and located at fixed
address locations. The operation of WBC and RBC is
shown in Figures 7a and 7b.
On the external memory port side, the device
performs 8-bit wide operations with a cycle time of
30 or 61 ns. The parallel port operates at 16.384
MByte/s (for mode 1) or 32.768 MByte/s (for modes
2,3,4 and 5). To create the high speed clock required
to manage the byte operations at the parallel port, a
built in PLL multiplies the serial port input clock
(SCLK) by a factor of two or four depending on the
mode. In all operation modes, the user should
connect the PLL CKout to PCLK input.
A separate input pin, Output Enable serial (OEser
pin 30), may be used to selectively tristate individual
64Kb/s serial links. By using a 9-bit external dual
MT90210
port RAM and connecting the ninth bit to OEser as
shown in Figure 9, the processor may disable an
individual channel by setting the ninth bit for that
channel in the transmit (TX) portion of the current
block. The remaining 8 bits for this channel may be
any value since they are ignored by the MT90210
when the ninth bit is 1. To avoid contention on the
serial bus, it is recommend that the user configure all
serial streams as inputs at start-up. This may be
done by setting all OEser bits to 1 in the TX portions
of both memory blocks. In mode 3, the serial streams
are permanently configured as 12 inputs and 12
outputs, and the state of OEser is ignored.
An Overview of CTI bus protocols
Multi-Vendor Integration Protocol (MVIP) provides a
coherent approach to building solutions for
worldwide markets by merging computing and
communications technologies under one open
architecture. MVIP ensures inter-operability among
telephone-based
resources
(such
as
trunk
interfaces, voice, video, fax, text-to-speech, speech
recognition) for use within a computer chassis in an
individual or networked configuration. H-MVIP
addresses the need for higher telephony traffic
capacity in individual computer chassis. H-MVIP
defines three major items that together make a
useful digital telephony transport and switching
environment: the H-MVIP digital telephony bus with
up to 3072 "time-slots" of 64 Kb/s each; a bus
interface with digital switching that allows a group of
H-MVIP interfaced circuit boards to provide
complete, flexible, distributed telephony switching;
and a logical device driver model and standard
software interface to a logical model.
Operating Modes
The MT90210 device can operate in one of five
modes appropriate for different application needs.
Mode selection must be done while the device is in
reset (RST low and a valid clock applied to the PCLK
input). These modes are explained in the following
paragraphs.
Mode 1:
The serial input/output format conforms to
the ST-BUS requirements when the data rate is
2.048 Mb/s (see Figure 6). Serial port clock (SCLK)
is 4.096 MHz. The on-chip PLL produces a phase
locked 16.384 MHz clock (CKout) from the SCLK
input. In this data rate operation, the 24 serial lines
(S0-23) become bidirectional links at 2.048 Mb/s.
The ST-BUS is a time-division multiplexed serial bus
with 32, 8-bit channels per frame. Frame boundaries
are delineated by the frame pulse. Figure 3 depicts
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