MM74HC161 • MM74HC163 Synchronous Binary Counter with Asynchronous Clear • Synchronous Binary
Counter with Synchronous Clear
September 1983
Revised February 1999
MM74HC161 • MM74HC163
Synchronous Binary Counter with Asynchronous Clear
• Synchronous Binary Counter with Synchronous Clear
General Description
The MM74HC161 and MM74HC163 synchronous presetta-
ble counters utilize advanced silicon-gate CMOS technol-
ogy and internal look-ahead carry logic for use in high
speed counting applications. They offer the high noise
immunity and low power consumption inherent to CMOS
with speeds similar to low power Schottky TTL. The HC161
and the HC163 are 4 bit binary counters. All flip-flops are
clocked simultaneously on the LOW-to-HIGH transition
(positive edge) of the CLOCK input waveform.
These counters may be preset using the LOAD input. Pre-
setting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held LOW counting is disabled
and the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken HIGH before the positive edge of CLOCK the count
operation will be unaffected.
All of these counters may be cleared by utilizing the
CLEAR input. The clear function on the MM74HC163
counter is synchronous to the clock. That is, the counters
are cleared on the positive edge of CLOCK while the clear
input is held LOW.
The MM74HC161 counter is cleared asynchronously.
When the CLEAR is taken LOW the counter is cleared
immediately regardless of the CLOCK.
Two active HIGH enable inputs (ENP and ENT) and a RIP-
PLE CARRY (RC) output are provided to enable easy cas-
cading of counters. Both ENABLE inputs must be HIGH to
count. The ENT input also enables the RC output. When
enabled, the RC outputs a positive pulse when the counter
overflows. This pulse is approximately equal in duration to
the HIGH level portion of the Q
A
output. The RC output is
fed to successive cascaded stages to facilitate easy imple-
mentation of N-bit counters.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical operating frequency: 40 MHz
s
Typical propagation delay; clock to Q: 18 ns
s
Low quiescent current: 80
µA
maximum (74HC Series)
s
Low input current: 1
µA
maximum
s
Wide power supply range: 2–6V
Ordering Code:
Order Number
MM74HC161M
MM74HC161SJ
MM74HC161MTC
MM74HC161N
MM74HC163M
MM74HC163SJ
MM74HC163MTC
MM74HC163N
Package Number
M16A
M16D
MTC16
N16E
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS005008.prf
www.fairchildsemi.com
MM74HC161 • MM74HC163
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin
(I
OUT
)
(I
CC
)
DC V
CC
or GND Current, per pin
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature
(T
L
) (Soldering 10 seconds)
260°C
600 mW
500 mW
−0.5
to
+7.0V
−1.5
to V
CC
+1.5V
−0.5
to V
CC
+0.5V
±20
mA
±25
mA
±50
mA
−65°C
to
+150°C
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
−40
+85
°C
2
0
Max
6
V
CC
Units
V
V
Storage Temperature Range (T
STG
)
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
T
A
=−40
to 85°C T
A
=−55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
6.0V
V
IN
=
V
CC
or GND
4.5V
6.0V
6.0V
4.5V
6.0V
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=5.5V
and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current
(I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
www.fairchildsemi.com
MM74HC161 • MM74HC163
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
t
REM
t
S
t
H
t
W
Parameter
Maximum Operating Frequency
Maximum Propagation Delay, Clock to RC
Maximum Propagation Delay, Clock to Q
Maximum Propagation Delay, ENT to RC
Maximum Propagation Delay, Clear to Q or RC
Minimum Removal Time, Clear to Clock
Minimum Set Up Time Clear, Load,
Enable or Data to Clock
Minimum Hold Time, Data from Clock
Minimum Pulse Width Clock,
Clear, or Load
5
16
ns
ns
Conditions
Typ
43
30
29
18
27
10
Guaranteed Limit
30
35
34
32
38
20
30
Units
MHz
ns
ns
ns
ns
ns
ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns
(unless otherwise specified)
Symbol
f
MAX
Parameter
Maximum Operating
Frequency
t
PHL
Maximum Propagation
Delay, Clock to RC
t
PLH
Maximum Propagation
Delay, Clock to RC
t
PHL
Maximum Propagation
Delay, Clock to Q
t
PLH
Maximum Propagation
Delay, Clock to Q
t
PHL
Maximum Propagation
Delay, ENT to RC
t
PLH
Maximum Propagation
Delay, ENT to RC
t
PHL
Maximum Propagation
Delay, Clear to RC
t
PHL
Maximum Propagation
Delay, Clear to Q
t
REM
Minimum Removal
Time Clear to Clock
t
S
Minimum Setup
Time Clear or Data
to Clock
t
S
Minimum Setup
Time Load
to Clock
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=25°C
Typ
10
40
45
100
32
28
88
18
15
95
30
26
85
17
14
90
28
24
80
16
14
100
32
28
100
32
28
5
27
32
215
43
37
175
35
30
205
41
35
170
34
29
195
39
33
160
32
27
220
44
37
210
42
36
125
25
21
150
30
26
135
27
23
T
A
=−40
to 85°C T
A
=−55
to 125°C
Guaranteed Limits
4
21
25
271
54
46
220
44
37
258
52
44
214
43
36
246
49
42
202
40
34
275
55
47
260
52
45
158
32
27
190
38
32
170
34
29
4
18
21
320
64
54
260
52
44
305
61
52
253
51
43
291
58
49
238
48
41
325
66
55
315
63
54
186
37
32
225
45
38
200
41
35
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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