TDA8263HN
Fully integrated satellite tuner
Rev. 01 — 14 December 2004
Product data sheet
1. General description
The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV
broadcasting, satisfying both DVB-S and DBS TV standards. The wide range oscillator
(from 950 MHz to 2175 MHz) covers the American, European and Asian satellite bands,
as well as the SMA-TV US standard.
The Zero-IF (ZIF) concept discards traditional IF filtering and intermediate conversion
techniques.
Gain-controlled amplifiers in the RF guarantee optimum signal level. The variable gain is
controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and
applied to pin AGC.
The integrated LNA allows the IC to be directly connected to the LNB output. The LNA can
be by-passed by an I
2
C-bus selectable attenuation, providing a 20 dB extra attenuation in
order to handle higher input signal levels of up to 0 dBm per channel.
Connected at the RF input, an RMS level detector provides through I
2
C-bus read mode
the full band input signal level.
The LO quadrature outputs are derived from a high performance integrated LC oscillator.
f
LO
f
XTAL
Its frequency is: --------
=
-------------- . Thanks to the low phase noise performance of the
-
-
N
R
integrated LC oscillator which controls the LO frequency, the synthesizer offers a good
performance for phase noise in the satellite band. The step size of the LO output
frequency is equal to the comparison frequency.
Control data is entered via the I
2
C-bus. The bus can be either 5.0 V or 3.3 V, allowing
compatibility with most of existing microcontrollers.
An 8-byte frame is required to address the device and to program the main divider ratio,
the reference divider ratio, the charge-pump current and the operating mode.
A flag is set when the loop is in-lock, readable during read operations, as well as the
Power-on reset flag and RF input level.
The device has four selectable I
2
C-bus addresses. Applying a specific voltage to pin AS
selects an address. This feature gives the possibility to use up to four TDA8263HN ICs in
the same system.
Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
2. Features
s
s
s
s
Direct conversion QPSK and 8PSK demodulation (ZIF)
3.3 V DC supply voltage (no 30 V required)
950 MHz to 2175 MHz frequency range
High range input level;
x
−70
dBm to
−15
dBm at 75
Ω
(normal mode)
x
Up to 0 dBm (20 dB attenuation configuration).
Low noise RF input (integrated LNA)
0 dB to 55 dB continuous variable gain on RF input
RF input level detector
Switchable 0 dB to 9 dB additional gain on baseband output amplifier
High AGC linearity (< 0.7 dB/step when used with an 8-bit DAC), AGC controlled
voltage between 0.3 V and 3 V
Programmable 5 MHz to 36 MHz 5th-order baseband filters for I and Q paths
Fully integrated PLL frequency synthesizer
Low phase noise fully integrated oscillator
Operation from a 16 MHz crystal or external clock
5 frequency steps from 125 kHz to 2 MHz
Crystal frequency output to drive the demodulator IC
Compatible with 5 V and 3.3 V I
2
C-bus
Fully compatible and easy to interface with the PS digital satellite demodulators family
32-pin low thermal resistance package.
s
s
s
s
s
s
s
s
s
s
s
s
s
s
3. Applications
s
s
s
s
Direct Broadcasting Satellite (DBS) QPSK demodulation
Digital Video Broadcasting (DVB) QPSK demodulation
BS digital 8PSK demodulation
DVB-S2 8PSK demodulation.
4. Quick reference data
Table 1:
Symbol
V
CC
I
CC
f
osc
∆Φ
V
o(I/Q)(rms)
Quick reference data
Parameter
supply voltage
supply current
oscillator frequency
absolute quadrature
error
recommended I and Q
output voltage RMS
value (QPSK signals)
LPF cut-off frequency
5-bit controlled
measured at 10 MHz
[1]
Conditions
Min
3.15
-
950
0
-
Typ
3.3
167
-
-
200
Max
3.45
-
2175
5
-
Unit
V
mA
MHz
degree
mV
f
LPF
-
5 to 36 -
MHz
9397 750 13193
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2004
2 of 28
Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Quick reference data
…continued
Parameter
Conditions
[2]
Table 1:
Symbol
ΦN
osc
SNF
SB
AGC
T
amb
[1]
[2]
Min
-
-
55
−20
Typ
−100
-
60
-
Max
−94
−78
-
+85
Unit
dBc/Hz
dBc/Hz
dB
°C
oscillator phase noise in 100 kHz offset;
the satellite band
f
comp
= 1 MHz
synthesizer noise floor in 1 kHz and10 kHz
the satellite band
offset; f
comp
= 1 MHz
amplifier gain control
range
ambient temperature
[2]
The product is qualified with an output voltage of 550 mV (p-p) differential, however larger values can be
used at baseband outputs that might have impact on the product performance.
Phase noise in optimal conditions, see related application note.
5. Typical performances
•
Noise figure at maximum gain: 8 dB
•
High linearity:
–
IIP
2
= +2 dBm at
−20
dBm input and 2.15 GHz
–
IIP
3
= +6 dBm at
−20
dBm input and 2.15 GHz.
•
Low synthesizer noise floor:
−78
dBc/Hz at 1 kHz and 10 kHz offset with
f
comp
= 1 MHz
•
•
•
•
AGC linearity: < 0.7 dB/step with a 8-bit DAC
Maximum I/Q amplitude mismatch: 1 dB
Maximum I/Q quadrature mismatch: 5°
Symbol rates: from 1 MBd to 45 MBd.
6. Ordering information
Table 2:
Ordering information
Package
Name
TDA8263HN
HVQFN32
Description
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
×
5
×
0.85 mm
Version
SOT617-1
Type number
9397 750 13193
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2004
3 of 28
Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
7. Block diagram
AGC
9
4
2
LNA
RFIN
3
11
AGC
control
1
5
3
PORT0
8
PORT1
32
10
15
V
CC(BB)
GND(BB)
V
CC(LNA)
GND(LNA)
TDA8263HN
5 MHz to 36 MHz filter
0 dB to +9 dB
variation gain
14
13
IP
IN
ATT
V
CC(RF)
GND(RF)
7
5
12
QP
QN
3
LEVEL
DETECTOR
0°
90°
GND(DIE)
1
LATCH
AND
CONTROL BIT
I
2
C-BUS
INTERFACE
29
30
17
SDA
SCL
AS
15-BIT DIVIDER
XTOUT
15
3
25
XTOUT
N2
×
N1
I/Q outputs
wide band
integrated
oscillator
n.c.
6
19
V
CC(VCO)
GND(VCO)
21
23
V
CC(PLL)
LOW-NOISE
INTEGRATED
LC OSCILLATOR
26
REFERENCE
DIVIDER
CRYSTAL
OSCILLATOR
27
16
XT
XTN
MS
3, 2
LOCK
DETECTOR
24
18
CAPVCO
20
22
1
POWER-ON
RESET
28
31
1
VT CP
V
CC(DIG)
GND(DIG)
001aaa974
GND(PLL)
Fig 1. Block diagram
9397 750 13193
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2004
4 of 28
Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
8. Pinning information
8.1 Pinning
31 GND(DIG)
28 V
CC(DIG)
27 XTN
GND(DIE)
GND(LNA)
RFIN
V
CC(LNA)
GND(RF)
n.c.
V
CC(RF)
PORT0
1
2
3
4
5
6
7
8
V
CC(BB)
10
QP 11
QN 12
IN 13
IP 14
GND(BB) 15
MS 16
9
26 XT
terminal 1
index area
25 XTOUT
24 GND(PLL)
23 V
CC(PLL)
22 CP
21 GND(VCO)
20 VT
19 V
CC(VCO)
18 CAPVCO
17 AS
32 PORT1
TDA8263HN
AGC
29 SDA
30 SCL
001aaa976
Transparent top view
Fig 2. Pin configuration
8.2 Pin description
Table 3:
Symbol
GND(DIE)
GND(LNA)
RFIN
V
CC(LNA)
GND(RF)
n.c.
V
CC(RF)
PORT0
AGC
V
CC(BB)
QP
QN
IN
IP
GND(BB)
MS
AS
CAPVCO
9397 750 13193
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Description
isolation ground
LNA ground
RF input
LNA supply voltage
RF ground
not connected
RF supply voltage
pull-down port 0
automatic gain control input
baseband supply voltage
Q positive output
Q negative output
I negative output
I positive output
baseband ground
master/slave crystal oscillator mode input
address select input
internal LC VCO regulation capacitor
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2004
5 of 28
京公网安备 11010802033920号
EEWORLD
