TDA8932
Class-D audio amplifier
Rev. 02 — 12 December 2006
Preliminary data sheet
1. General description
The TDA8932 is a high efficiency class-D amplifier with low power dissipation.
The typical output power is 2
×
15 W in stereo half-bridge application (R
L
= 4
Ω)
or
1
×
30 W typical in full-bridge application (R
L
= 8
Ω).
Due to the low power dissipation the
device can be used without any external heat sink when playing music. If proper cooling
via the printed-circuit board is implemented, a continuous output power of 2
×
15 W is
feasible. Due to the implementation of thermal foldback, even for high supply voltages
and/or lower load impedances, the device remains operating with considerable music
output power without the need for an external heat sink.
The device has two full-differential inputs driving two independent outputs. It can be used
as mono full-bridge configuration (BTL) or as stereo half-bridge configuration (SE).
2. Features
Operating voltage from 10 V to 36 V asymmetrical or
±5
V to
±18
V symmetrical
Mono-bridged tied load (full-bridge) or stereo single-ended (half-bridge) application
Application without heatsink using thermally enhanced small outline package
High efficiency and low-power dissipation
Thermally protected and thermal foldback
Current limiting to avoid audio holes
Full short-circuit proof across load and to supply lines (using advanced current
protection)
I
Switchable internal or external oscillator (master-slave setting)
I
No pop noise
I
Full-differential inputs
I
I
I
I
I
I
I
3. Applications
I
I
I
I
I
I
Flat panel television sets
Flat panel monitor sets
Multimedia systems
Wireless speakers
Mini and micro systems
Home sound sets
NXP Semiconductors
TDA8932
Class-D audio amplifier
4. Quick reference data
Table 1.
Quick reference data
V
P
= 22 V; f
osc
= 320 kHz; T
amb
= 25
°
C; unless otherwise specified.
Symbol Parameter
Supplies
V
P
I
P
I
q(tot)
supply voltage
supply current
total quiescent
current
asymmetrical supply
Sleep mode; no load
Operating mode; no load, no
snubbers and no filter
connected
continuous time output power
per channel;
THD+N = 10 %; f
i
= 1 kHz
R
L
= 4
Ω;
V
P
= 22 V
R
L
= 8
Ω;
V
P
= 30 V
short time output power per
channel; THD+N = 10 %;
f
i
= 1 kHz
R
L
= 4
Ω;
V
P
= 29 V
Mono BTL; R
s
< 0.1
Ω
[1][2]
P
o(RMS)
RMS output power
continuous time output power;
THD+N = 10 %; f
i
= 1 kHz
R
L
= 4
Ω;
V
P
= 12 V
R
L
= 8
Ω;
V
P
= 22 V
short time output power;
THD+N = 10 %; f
i
= 1 kHz
R
L
= 8
Ω;
V
P
= 29 V
[1]
[2]
Output power is measured indirectly; based on R
DSon
measurement.
R
s
is the series resistance of inductor of low-pass LC filter in the application.
Conditions
Min
10
-
-
Typ
22
0.6
40
Max
36
1
80
Unit
V
mA
mA
Stereo SE channel; R
s
< 0.1
Ω
[1][2]
P
o(RMS)
RMS output power
14
14
15
15
-
-
W
W
23
25
-
W
14
28
15
30
-
-
W
W
47
50
-
W
5. Ordering information
Table 2.
Ordering information
Package
Name
TDA8932T
SO32
Description
plastic small outline package; 32 leads;
body width 7.5 mm
Version
SOT287-1
Type number
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
2 of 45
NXP Semiconductors
TDA8932
Class-D audio amplifier
6. Block diagram
OSCREF
OSCIO
V
DDA
8
28
OSCILLATOR
DRIVER
HIGH
V
SSD
PWM
MODULATOR
CTRL
DRIVER
LOW
26
29
27
BOOT1
V
DDP1
OUT1
V
SSP1
10
31
IN1P
2
IN1N
INREF
IN2P
3
12
15
PWM
MODULATOR
14
PROTECTIONS:
OVP, OCP, OTP,
UVP, TF, WP
MANAGER
21
20
DRIVER
HIGH
CTRL
DRIVER
LOW
23
22
BOOT2
V
DDP2
OUT2
V
SSP2
IN2N
V
DDA
STABILIZER 11 V
25
STAB1
DIAG
4
V
DDA
V
SSP1
24
STABILIZER 11 V
CGND
7
V
SSP2
STAB2
POWERUP
6
REGULATOR 5 V
MODE
V
SSD
18
DREF
ENGAGE
5
V
DDA
11
HVPREF
30
HVP1
TEST
13
TDA8932
V
SSA
19
HVP2
HALF SUPPLY VOLTAGE
9
1, 16, 17, 32
001aad757
V
SSA
V
SSD(HW)
Fig 1. Block diagram
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
3 of 45
NXP Semiconductors
TDA8932
Class-D audio amplifier
7. Pinning information
7.1 Pinning
V
SSD(HW)
IN1P
IN1N
DIAG
ENGAGE
POWERUP
CGND
V
DDA
V
SSA
1
2
3
4
5
6
7
8
9
32 V
SSD(HW)
31 OSCIO
30 HVP1
29 V
DDP1
28 BOOT1
27 OUT1
26 V
SSP1
25 STAB1
24 STAB2
23 V
SSP2
22 OUT2
21 BOOT2
20 V
DDP2
19 HVP2
18 DREF
17 V
SSD(HW)
001aad756
TDA8932T
OSCREF 10
HVPREF 11
INREF 12
TEST 13
IN2N 14
IN2P 15
V
SSD(HW)
16
Fig 2. Pin configuration SO32
7.2 Pin description
Table 3.
Symbol
V
SSD(HW)
IN1P
IN1N
DIAG
ENGAGE
POWERUP
CGND
V
DDA
V
SSA
OSCREF
HVPREF
INREF
TEST
IN2N
IN2P
V
SSD(HW)
V
SSD(HW)
DREF
TDA8932_2
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Description
negative digital supply voltage and handle wafer connection
positive audio input for channel 1
negative audio input for channel 1
diagnostic output; open-drain
engage input to switch between Mute mode and Operating mode
power-up input to switch between Sleep mode and Mute mode
control ground; reference for POWERUP, ENGAGE and DIAG
positive analog supply voltage
negative analog supply voltage
input internal oscillator setting (only master setting)
decoupling of internal half supply voltage reference
decoupling for input reference voltage
test signal input; for testing purpose only
negative audio input for channel 2
positive audio input for channel 2
negative digital supply voltage and handle wafer connection
negative digital supply voltage and handle wafer connection
decoupling of internal (reference) 5 V regulator for logic supply
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
4 of 45
NXP Semiconductors
TDA8932
Class-D audio amplifier
Pin description
…continued
Pin
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Description
half supply output voltage 2 for charging single-ended capacitor for
channel 2
positive power supply voltage for channel 2
bootstrap high-side driver channel 2
PWM output channel 2
negative power supply voltage for channel 2
decoupling of internal 11 V regulator for channel 2 drivers
decoupling of internal 11 V regulator for channel 1 drivers
negative power supply voltage for channel 1
PWM output channel 1
bootstrap high-side driver channel 1
positive power supply voltage for channel 1
half supply output voltage 1 for charging single-ended capacitor for
channel 1
oscillator input in slave configuration or oscillator output in master
configuration
negative digital supply voltage and handle wafer connection
Table 3.
Symbol
HVP2
V
DDP2
BOOT2
OUT2
V
SSP2
STAB2
STAB1
V
SSP1
OUT1
BOOT1
V
DDP1
HVP1
OSCIO
V
SSD(HW)
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
5 of 45
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