INTEGRATED CIRCUITS
DATA SHEET
TDA6103Q
Triple video output amplifier
Preliminary specification
File under Integrated Circuits, IC02
March 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Triple video output amplifier
FEATURES
•
High bandwidth: 7.5 MHz typical; 60 V (peak-to-peak
value)
•
High slew rate: 1600 V/µs
•
Simple application with a variety of colour decoders
•
Only one supply voltage needed
•
Internal protection against positive appearing
Cathode-Ray Tube (CRT) flashover discharges
•
One non-inverting input with a low minimum input
voltage of 1 V
•
Thermal protection
•
Controllable switch-off behaviour.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
TDA6103Q
BLOCK DIAGRAM
VDD
6
VDD
MIRROR 2
VDD
VDD
VDD
TDA6103Q
GENERAL DESCRIPTION
The TDA6103Q includes three video output amplifiers in
one single in-line 9-pin medium power (SIL9MP) package
SOT111BE, using high-voltage DMOS technology,
intended to drive the three cathodes of a colour CRT.
PACKAGE
PINS
9
PIN POSITION
DBS9
MATERIAL
plastic
CODE
SOT111BE
3x
TDA6103Q
VDD
MIRROR 3
FLASH-
DIODE
Voc
(3x)
9,8,7
1x
Vbias
CURRENT
SOURCES
inverting
input
(3x)
1,2,3
LEVEL-
SHIFTER 1
DIFFERENTIAL
STAGE
LEVEL-
SHIFTER 2
5
non-inverting
input
Vip
MIRROR 1
THERMAL
PROTECTION
4
GND
MGA968
Fig.1 Block diagram (one amplifier shown).
March 1994
2
Philips Semiconductors
Preliminary specification
Triple video output amplifier
PINNING
SYMBOL
V
i1
V
i2
V
i3
GND
V
ip
V
DD
V
oc3
V
oc2
V
oc1
PIN
1
2
3
4
5
6
7
8
9
DESCRIPTION
inverting input 1
inverting input 2
inverting input 3
ground, fin
non-inverting input
supply voltage
cathode output 3
cathode output 2
cathode output 1
V i1
Vi2
Vi3
GND
Vip
V DD
Voc3
Voc2
V oc1
1
2
3
4
5
6
7
8
9
MGA969
TDA6103Q
TDA6103Q
Fig.2 Pin configuration.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages measured with respect to GND (pin 4);
currents as specified in Fig.1; unless otherwise specified.
SYMBOL
V
DD
V
i
V
idm
V
oc
I
ocsmL
I
ocsmH
T
stg
T
j
V
es
PARAMETER
supply voltage
input voltage
differential mode input voltage
cathode output voltage
LOW non-repetitive peak cathode
output current
HIGH non-repetitive peak cathode
output current
storage temperature
junction temperature
electrostatic handling
human body model (HBM)
machine model (MM)
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see
“Handling MOS Devices”).
QUALITY SPECIFICATION
Quality specification
“SNW-FQ-611 part E”
is applicable and can be found in the
“Quality reference pocketbook”
(ordering
number 9398 510 34011).
−
−
tbf
tbf
V
V
flashover discharge = 50
µC
flashover discharge = 100 nC
CONDITIONS
0
0
−6
0
0
0
−55
−20
MIN.
MAX.
250
12
+6
V
DD
5
10
+150
+150
V
V
V
V
A
A
°C
°C
UNIT
March 1994
3
Philips Semiconductors
Preliminary specification
Triple video output amplifier
THERMAL RESISTANCE
SYMBOL
R
th j-fin
R
th h-a
Note
1. An external heatsink is necessary.
Thermal protection
6
MGA972
TDA6103Q
PARAMETER
from junction to fin; note 1
from heatsink to ambient
THERMAL RESISTANCE
11 K/W
18 K/W
5
P tot
(W)
4
(1)
3
(2)
2
The internal thermal protection circuit gives a decrease of
the slew rate at high temperatures: 10% decrease at
130
°C
and 30% decrease at 145
°C
(typical values on the
spot of the thermal protection circuit).
OUTPUTS
1
5 K/W
Thermal protection circuit
0
–50
0
50
100
150
o C)
T amb (
FIN
6 K/W
MGA970
(1) Infinite heatsink.
(2) No heatsink.
Fig.3 Power derating curves.
Fig.4 Equivalent thermal resistance network.
March 1994
4
Philips Semiconductors
Preliminary specification
Triple video output amplifier
CHARACTERISTICS
Operating range: T
j
=
−20
to 150
°C;
V
DD
= 180 to 210 V; V
ip
= 1 to 4 V.
TDA6103Q
Test conditions (unless otherwise specified): T
amb
= 25
°C;
V
DD
= 200 V; V
ip
= 1.3 V; V
oc1
= V
oc2
= V
oc3
=
1
⁄
2
V
DD
;
C
L
= 10 pF (C
L
consists of parasitic and cathode capacitance); R
th h-a
= 18 K/W; measured in test circuit Fig.5.
SYMBOL
I
DD
I
bias
I
bias
V
i(offset)
PARAMETER
quiescent supply current
input bias current inverting inputs
(pins 1, 2 and 3)
input bias current non-inverting
input (pin 5)
input offset voltage
(pins 1, 2 and 3)
CONDITIONS
MIN.
7.0
−5
−15
−50
−
TYP.
9.25
−1
−3
−
tbf
MAX.
11.5
+1
+1
+50
−
UNIT
mA
µA
µA
mV
mV/K
∆V
i(offset)
differential input offset voltage
temperature drift between pins 1
and 5; 2 and 5; 3 and 5
C
icm
C
icm
C
idm
V
oc(min)
V
oc(max)
GB
common-mode input capacitance
(pins 1, 2 and 3)
common-mode input capacitance
(pin 5)
differential mode input capacitance
between 1 and 5; 2 and 5; 3 and 5
minimum output voltage
(pins 7, 8 and 9)
maximum output voltage
(pins 7, 8 and 9)
gain-bandwidth product of
open-loop gain:
V
oc1, 2, 3
/ V
i1-5, 2-5, 3-5
small signal bandwidth
(pins 7, 8 and 9)
large signal bandwidth
(pins 7, 8 and 9)
cathode output propagation delay
time 50% input to 50% output
(pins 7, 8 and 9)
difference in cathode output
propagation time 50% input to
50% output (pins 7 and 8, 7 and 9
and 8 and 9)
cathode output rise time 10%
output to 90% output
(pins 7, 8 and 9)
V
1−5
= V
2−5
= V
3−5
=
−1
V
V
1−5
= V
2−5
= V
3−5
= 1 V;
note 1
f = 500 kHz
−
−
−
−
5
10
1
5
−
−
−
10
−
−
pF
pF
pF
V
V
GHz
V
DD
−
10 V
DD
−
6
−
0.75
B
S
B
L
t
pd
V
oc(p-p)
= 60 V
V
oc(p-p)
= 100 V
V
oc(p-p)
= 100 V square
wave; f < 1 MHz;
t
r
= t
f
= 40 ns (pins 1, 2
and 3); see Figs 7 and 8
V
oc(p-p)
= 100 V square
wave; f < 1 MHz;
t
r
= t
f
= 40 ns (pins 1, 2
and 3)
6
5
−
7.5
7
38
−
−
−
MHz
MHz
ns
∆t
p
−10
0
+10
ns
t
r
V
oc
= 50 to 150 V square
48
wave; f < 1 MHz; t
f
= 40 ns
(pins 1, 2 and 3); see Fig.7
60
73
ns
t
f
cathode output fall time 90% output V
o
= 150 to 50 V square
48
to 10% output (pins 7, 8 and 9)
wave; f < 1 MHz; t
r
= 40 ns
(pins 1, 2 and 3); see Fig.8
60
73
ns
March 1994
5
京公网安备 11010802033920号
EEWORLD
